Home
last modified time | relevance | path

Searched refs:RO (Results 1 – 25 of 428) sorted by relevance

12345678910>>...18

/external/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td186 RegisterOperand RO> :
187 InstSE<(outs), (ins RO:$rs, opnd:$offset),
196 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
198 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
200 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
206 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
208 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
210 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
229 class MovePMM16<string opstr, RegisterOperand RO> :
230 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
[all …]
DMipsInstrInfo.td1096 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1099 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1101 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1108 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1112 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1114 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1130 class LogicNOR<string opstr, RegisterOperand RO>:
1131 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1133 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1139 RegisterOperand RO, InstrItinClass itin,
[all …]
DMicroMips64r6InstrInfo.td96 class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
99 dag OutOperandList = (outs RO:$rt);
100 dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
102 list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
173 class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
177 dag OutOperandList = (outs RO:$rd);
178 dag InOperandList = (ins RO:$rs, RO:$rt);
180 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
DMicroMipsDSPInstrInfo.td218 RegisterOperand RO, Operand ImmOpnd> {
219 dag OutOperandList = (outs RO:$rt);
220 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
222 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
254 InstrItinClass itin, RegisterOperand RO> {
255 dag OutOperandList = (outs RO:$rd);
256 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
258 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
337 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
340 dag InOperandList = (ins RO:$ac);
[all …]
DMipsDSPInstrInfo.td328 RegisterOperand RO> {
329 dag OutOperandList = (outs RO:$rd);
332 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
338 InstrItinClass itin, RegisterOperand RO> {
339 dag OutOperandList = (outs RO:$rd);
340 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
342 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
349 RegisterOperand RO, Operand ImmOpnd> {
350 dag OutOperandList = (outs RO:$rd);
351 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
[all …]
DMips64InstrInfo.td354 class Count1s<string opstr, RegisterOperand RO>:
355 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
356 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
387 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
388 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
390 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
398 class MFC2OP<string asmstr, RegisterOperand RO> :
399 InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
749 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
750 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
DMicroMips32r6InstrInfo.td454 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
455 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
456 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
486 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
487 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
643 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
647 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
648 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
655 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
657 dag InOperandList = (ins RO:$rs);
[all …]
/external/ltp/testcases/kernel/fs/fs_readonly/
Dtest_robind.sh143 local RO=$3
158 if [ "$RO" = "false" -a $tst_result -ne 0 -o "$RO" = "true" -a \
163 $dir $fs_type read-only flag: $RO"
166 $dir $fs_type read-only flag: $RO"
/external/autotest/server/site_tests/firmware_RONormalBoot/
Dcontrol9 PURPOSE = "Servo based firmware RO normal boot test"
10 CRITERIA = "This test will fail if disabling RO normal boot flag boots failed"
19 This test disables the RO normal boot flag and checks the next boot result.
Dcontrol.dev9 PURPOSE = "Servo based firmware RO normal boot test"
10 CRITERIA = "This test will fail if disabling RO normal boot flag boots failed"
19 This test disables the RO normal boot flag and checks the next boot result.
Dcontrol.ec_wp9 PURPOSE = "Servo based firmware RO normal boot test"
10 CRITERIA = "This test will fail if disabling RO normal boot flag boots failed"
20 This test disables the RO normal boot flag and checks the next boot result.
/external/autotest/server/site_tests/firmware_ECWriteProtect/
Dcontrol20 This test starts with RO normal mode and enables EC write protect. Software sync
28 - Cold reset. RO normal.
32 RO normal mode.
Dcontrol.dev20 This test starts with RO normal mode and enables EC write protect. Software sync
28 - Cold reset. RO normal.
32 RO normal mode.
/external/python/cpython3/Lib/test/
Dtest_enum.py1719 RO = 0 variable in TestFlag.Open
1741 self.assertEqual(str(Open.RO), 'Open.RO')
1744 self.assertEqual(str(Open.RO | Open.CE), 'Open.CE')
1746 self.assertEqual(str(~Open.RO), 'Open.CE|AC|RW|WO')
1749 self.assertEqual(str(~(Open.RO | Open.CE)), 'Open.AC')
1768 self.assertEqual(repr(Open.RO), '<Open.RO: 0>')
1771 self.assertEqual(repr(Open.RO | Open.CE), '<Open.CE: 524288>')
1773 self.assertEqual(repr(~Open.RO), '<Open.CE|AC|RW|WO: 524291>')
1776 self.assertEqual(repr(~(Open.RO | Open.CE)), '<Open.AC: 3>')
1789 self.assertIs(Open.RO | Open.CE, Open.CE)
[all …]
/external/python/cpython2/Modules/_sqlite/
Dconnection.c1632 {"Warning", T_OBJECT, offsetof(pysqlite_Connection, Warning), RO},
1633 {"Error", T_OBJECT, offsetof(pysqlite_Connection, Error), RO},
1634 {"InterfaceError", T_OBJECT, offsetof(pysqlite_Connection, InterfaceError), RO},
1635 {"DatabaseError", T_OBJECT, offsetof(pysqlite_Connection, DatabaseError), RO},
1636 {"DataError", T_OBJECT, offsetof(pysqlite_Connection, DataError), RO},
1637 {"OperationalError", T_OBJECT, offsetof(pysqlite_Connection, OperationalError), RO},
1638 {"IntegrityError", T_OBJECT, offsetof(pysqlite_Connection, IntegrityError), RO},
1639 {"InternalError", T_OBJECT, offsetof(pysqlite_Connection, InternalError), RO},
1640 {"ProgrammingError", T_OBJECT, offsetof(pysqlite_Connection, ProgrammingError), RO},
1641 {"NotSupportedError", T_OBJECT, offsetof(pysqlite_Connection, NotSupportedError), RO},
/external/swiftshader/third_party/LLVM/lib/Analysis/
DScalarEvolutionNormalization.cpp185 const SCEV *RO = X->getRHS(); in TransformImpl() local
187 const SCEV *RN = TransformSubExpr(RO, User, OperandValToReplace); in TransformImpl()
188 if (LO != LN || RO != RN) in TransformImpl()
/external/llvm/lib/Analysis/
DScalarEvolutionNormalization.cpp215 const SCEV *RO = X->getRHS(); in TransformImpl() local
217 const SCEV *RN = TransformSubExpr(RO, User, OperandValToReplace); in TransformImpl()
218 if (LO != LN || RO != RN) in TransformImpl()
/external/python/cpython2/Modules/
Dsunaudiodev.c359 { "i_open", T_UBYTE, OFF(record.open) , RO},
360 { "i_active", T_UBYTE, OFF(record.active) , RO},
378 { "o_open", T_UBYTE, OFF(play.open) , RO},
379 { "o_active", T_UBYTE, OFF(play.active) , RO},
Dflmodule.c275 {"objclass", T_INT, OFF(objclass), RO},
276 {"type", T_INT, OFF(type), RO},
289 {"pushed", T_INT, OFF(pushed), RO},
290 {"focus", T_INT, OFF(focus), RO},
291 {"belowmouse", T_INT, OFF(belowmouse),RO},
295 {"visible", T_INT, OFF(visible), RO},
1549 {"window", T_LONG, OFF(window), RO},
1552 {"x", T_FLOAT, OFF(x), RO},
1553 {"y", T_FLOAT, OFF(y), RO},
1555 {"visible", T_INT, OFF(visible), RO},
[all …]
/external/python/cpython2/Objects/
Dgenobject.c318 {"gi_frame", T_OBJECT, offsetof(PyGenObject, gi_frame), RO},
319 {"gi_running", T_INT, offsetof(PyGenObject, gi_running), RO},
320 {"gi_code", T_OBJECT, offsetof(PyGenObject, gi_code), RO},
Dframeobject.c18 {"f_back", T_OBJECT, OFF(f_back), RO},
19 {"f_code", T_OBJECT, OFF(f_code), RO},
20 {"f_builtins", T_OBJECT, OFF(f_builtins),RO},
21 {"f_globals", T_OBJECT, OFF(f_globals), RO},
22 {"f_lasti", T_INT, OFF(f_lasti), RO},
/external/llvm/test/Transforms/ObjCARC/
Drle-s2l.ll60 ; CHECK-NEXT: call void @use_pointer(i8* %x) [[RO:#[0-9]+]]
77 ; CHECK-NEXT: call void @use_pointer(i8* %x) [[RO]]
138 ; CHECK: attributes [[RO]] = { readonly }
/external/llvm/lib/Target/Hexagon/
DHexagonEarlyIfConv.cpp783 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
785 SR = RO.getReg(), SSR = RO.getSubReg(); in updatePhiNodes()
787 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
789 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()
DHexagonGenInsert.cpp361 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} in OrderedRegisterList() argument
483 void buildOrderingMF(RegisterOrdering &RO) const;
484 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
551 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { in buildOrderingMF()
567 RO.insert(std::make_pair(R, Index++)); in buildOrderingMF()
579 RegisterOrdering &RO) const { in buildOrderingBT()
591 RO.insert(std::make_pair(VRs[i], i)); in buildOrderingBT()
/external/python/cpython2/Include/
Dstructmember.h81 #define RO READONLY /* Shorthand */ macro

12345678910>>...18