| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | intrinsic_integer.inl | 40 __m128i Reg1; local
45 //Reg1 = _mm_unpacklo_epi64(x, y);
46 Reg1 = x;
50 Reg2 = _mm_slli_si128(Reg1, 2);
51 Reg1 = _mm_or_si128(Reg2, Reg1);
52 Reg1 = _mm_and_si128(Reg1, Mask4);
56 Reg2 = _mm_slli_si128(Reg1, 1);
57 Reg1 = _mm_or_si128(Reg2, Reg1);
58 Reg1 = _mm_and_si128(Reg1, Mask3);
62 Reg2 = _mm_slli_epi32(Reg1, 4);
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 447 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
464 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
483 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
493 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
95 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
98 GPRRegister::Encoded_Reg_##Reg1); \ in TEST_F()
101 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
107 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
120 GPRRegister::Encoded_Reg_##Reg1 < 4) { \ in TEST_F()
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
97 __ mov(IceType_i##Size, Encoded_GPR_##Reg1(), Immediate(Value1)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
100 __ And(IceType_i32, Encoded_GPR_##Reg1(), Immediate(Mask##Size)); \ in TEST_F()
105 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} in RegPairInfo()
875 unsigned Reg1; member
905 RPI.Reg1 = CSI[i].getReg(); in computeCalleeSaveRegisterPairs()
907 assert(AArch64::GPR64RegClass.contains(RPI.Reg1) || in computeCalleeSaveRegisterPairs()
908 AArch64::FPR64RegClass.contains(RPI.Reg1)); in computeCalleeSaveRegisterPairs()
909 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()
934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
935 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
974 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
992 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1); in spillCalleeSavedRegisters()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
614 uint16_t Reg1; variable
616 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
620 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
636 Reg0 = Reg1;
637 Reg1 = 0;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 769 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
778 unsigned Temp = Reg1; in EmitInstrRegReg()
779 Reg1 = Reg2; in EmitInstrRegReg()
783 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
789 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
793 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
800 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
804 unsigned temp = Reg1; in EmitMovFPIntPair()
805 Reg1 = Reg2; in EmitMovFPIntPair()
808 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
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| D | MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsTargetStreamer.h | 111 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
113 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
115 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
117 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
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| D | Mips16InstrInfo.cpp | 263 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
272 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
276 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
277 MIB3.addReg(Reg1); in adjustStackPtrBig()
281 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
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| D | MipsSEFrameLowering.cpp | 440 unsigned Reg1 = in emitPrologue() local
444 std::swap(Reg0, Reg1); in emitPrologue()
452 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
457 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
460 std::swap(Reg0, Reg1); in emitPrologue()
468 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 78 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
84 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
91 Reg0 = Reg1; in commuteInstruction()
102 .addReg(Reg1, getKillRegState(Reg2IsKill)); in commuteInstruction()
106 .addReg(Reg1, getKillRegState(Reg2IsKill)); in commuteInstruction()
111 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { in addRegReg() argument
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0) in addRegReg()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
174 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
183 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
189 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
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| D | MipsMCCodeEmitter.cpp | 130 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch() local
133 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
134 if (Reg0 < Reg1) in LowerCompactBranch()
137 if (Reg0 >= Reg1) in LowerCompactBranch()
141 if (Reg1 >= Reg0) in LowerCompactBranch()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 85 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
86 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 144 unsigned Reg1, bool isKill1, in addRegReg() argument
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 226 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
250 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
265 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in tryInlineAsm()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 515 unsigned Reg1 = Reg; in lowerCRSpilling() local
520 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
560 unsigned Reg1 = Reg; in lowerCRRestore() local
566 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
604 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
609 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1477 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1481 printRegName(O, Reg1); in printVectorListTwo()
1490 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1494 printRegName(O, Reg1); in printVectorListTwoSpaced()
1545 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1549 printRegName(O, Reg1); in printVectorListTwoAllLanes()
1592 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1596 printRegName(O, Reg1); in printVectorListTwoSpacedAllLanes()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1603 StringRef Reg1(R1); in processInstruction() local
1604 MO.setReg(matchRegister(Reg1)); in processInstruction()
1618 StringRef Reg1(R1); in processInstruction() local
1619 MO.setReg(matchRegister(Reg1)); in processInstruction()
1634 StringRef Reg1(R1); in processInstruction() local
1635 MO.setReg(matchRegister(Reg1)); in processInstruction()
1974 StringRef Reg1(R1); in processInstruction() local
1975 Rss.setReg(matchRegister(Reg1)); in processInstruction()
2128 StringRef Reg1(R1); in processInstruction() local
2129 Rss.setReg(matchRegister(Reg1)); in processInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 118 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
125 if (Reg0 == Reg1) { in commuteInstruction()
144 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
151 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 86 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
87 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 586 …bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1,…
804 …sterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum) in AddNextRegisterToList() argument
808 …if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { Reg = AMDGPU::EXEC; RegWidth = 2; return … in AddNextRegisterToList()
809 …if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { Reg = AMDGPU::FLAT_SCR; RegWidth … in AddNextRegisterToList()
810 …if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { Reg = AMDGPU::VCC; RegWidth = 2; return tru… in AddNextRegisterToList()
811 …if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { Reg = AMDGPU::TBA; RegWidth = 2; return tru… in AddNextRegisterToList()
812 …if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { Reg = AMDGPU::TMA; RegWidth = 2; return tru… in AddNextRegisterToList()
817 if (Reg1 != Reg + RegWidth) { return false; } in AddNextRegisterToList()
891 unsigned Reg1, RegNum1, RegWidth1; in ParseAMDGPURegister() local
898 } else if (ParseAMDGPURegister(RegKind1, Reg1, RegNum1, RegWidth1)) { in ParseAMDGPURegister()
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