Searched refs:RegHi (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
870 RegHi = RegLo; in ParseAMDGPURegister()
872 if (getParser().parseAbsoluteExpression(RegHi)) in ParseAMDGPURegister()
880 RegWidth = (RegHi - RegLo) + 1; in ParseAMDGPURegister()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 913 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
925 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
926 .addReg(RegHi) in expandPostRAPseudo()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 874 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
876 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3885 Variable *RegHi, *RegLo; in lowerCast() local
3890 RegHi = legalizeToReg(Ctx->getConstantInt32(Upper32Bits)); in lowerCast()
3891 _mov(Dest, RegHi, RegLo); in lowerCast()
3895 auto *RegHi = legalizeToReg(hiOperand(Var64On32)); in lowerCast() local
3896 _mov(Dest, RegHi, RegLo); in lowerCast()
|