/external/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 114 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument 115 if (WorklistMembers.test(RegIdx)) in PutInWorklist() 117 WorklistMembers.set(RegIdx); in PutInWorklist() 118 Worklist.push_back(RegIdx); in PutInWorklist() 366 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); in determineInitialDefinedLanes() local 367 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes() 368 PutInWorklist(RegIdx); in determineInitialDefinedLanes() 499 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local 500 unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); in runOnce() 503 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce() [all …]
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D | SplitKit.cpp | 384 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument 390 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue() 397 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), in defValue() 420 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { in forceRecompute() argument 422 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; in forceRecompute() 435 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in forceRecompute() 441 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument 448 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent() 452 bool Late = RegIdx != 0; in defFromParent() 455 unsigned Original = VRM.getOriginal(Edit->get(RegIdx)); in defFromParent() [all …]
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D | SplitKit.h | 324 LiveRangeCalc &getLRCalc(unsigned RegIdx) { in getLRCalc() argument 325 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; in getLRCalc() 333 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx); 339 void forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI); 343 VNInfo *defFromParent(unsigned RegIdx,
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D | LiveVariables.cpp | 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { in getVarInfo() argument 86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && in getVarInfo() 88 VirtRegInfo.grow(RegIdx); in getVarInfo() 89 return VirtRegInfo[RegIdx]; in getVarInfo()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | SplitKit.cpp | 345 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument 351 LiveInterval *LI = Edit->get(RegIdx); in defValue() 358 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), in defValue() 381 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { in forceRecompute() argument 383 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; in forceRecompute() 396 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI)); in forceRecompute() 401 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument 408 LiveInterval *LI = Edit->get(RegIdx); in defFromParent() 412 bool Late = RegIdx != 0; in defFromParent() 429 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def); in defFromParent() [all …]
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D | SplitKit.h | 289 LiveRangeCalc &getLRCalc(unsigned RegIdx) { in getLRCalc() argument 290 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; in getLRCalc() 298 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx); 304 void forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI); 308 VNInfo *defFromParent(unsigned RegIdx,
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D | LiveVariables.cpp | 81 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { in getVarInfo() argument 82 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && in getVarInfo() 84 VirtRegInfo.grow(RegIdx); in getVarInfo() 85 return VirtRegInfo[RegIdx]; in getVarInfo()
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/external/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 626 struct RegIdxOp RegIdx; member 640 Op->RegIdx.Index = Index; in CreateReg() 641 Op->RegIdx.RegInfo = RegInfo; in CreateReg() 642 Op->RegIdx.Kind = RegKind; in CreateReg() 652 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg() 653 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg() 655 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg() 661 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg() 663 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPRMM16Reg() 669 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR64Reg() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMCallingConv.h | 210 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local 215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate() 216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate() 251 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local 253 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate() 256 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
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D | ARMISelLowering.cpp | 3247 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); in LowerFormalArguments() local 3248 if (RegIdx != array_lengthof(GPRArgRegs)) in LowerFormalArguments() 3249 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); in LowerFormalArguments()
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
D | AMDGPUInstPrinter.cpp | 236 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); in printRegOperand() local 275 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen. in printRegOperand() 279 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen. in printRegOperand() 286 O << RegIdx; in printRegOperand() 290 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; in printRegOperand()
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/external/llvm/lib/Target/Mips/ |
D | MipsSEISelDAGToDAG.cpp | 72 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg() 73 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) { in getMSACtrlReg() 821 SDValue RegIdx = Node->getOperand(2); in trySelect() local 823 getMSACtrlReg(RegIdx), MVT::i32); in trySelect() 854 SDValue RegIdx = Node->getOperand(2); in trySelect() local 857 getMSACtrlReg(RegIdx), Value); in trySelect()
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D | MipsSEISelDAGToDAG.h | 34 unsigned getMSACtrlReg(const SDValue RegIdx) const;
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/external/llvm/lib/Target/AMDGPU/ |
D | SILowerControlFlow.cpp | 615 int RegIdx = BaseRegIdx + Offset; in computeIndirectRegAndOffset() local 616 if (RegIdx < 0) { in computeIndirectRegAndOffset() 617 Offset = RegIdx; in computeIndirectRegAndOffset() 618 RegIdx = 0; in computeIndirectRegAndOffset() 623 unsigned Reg = RC->getRegister(RegIdx); in computeIndirectRegAndOffset()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | LiveVariables.h | 281 VarInfo &getVarInfo(unsigned RegIdx);
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/external/llvm/include/llvm/CodeGen/ |
D | LiveVariables.h | 274 VarInfo &getVarInfo(unsigned RegIdx);
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/external/llvm/lib/Target/X86/ |
D | X86FastISel.cpp | 2480 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall() local 2481 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx); in fastLowerIntrinsicCall()
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 5745 unsigned RegIdx = 3; in shouldOmitPredicateOperand() local 5752 RegIdx = 4; in shouldOmitPredicateOperand() 5754 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand() 5756 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand() 5758 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
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