Home
last modified time | relevance | path

Searched refs:RegScavenger (Results 1 – 25 of 133) sorted by relevance

123456

/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterScavenging.cpp37 void RegScavenger::setUsed(unsigned Reg) { in setUsed()
45 bool RegScavenger::isAliasUsed(unsigned Reg) const { in isAliasUsed()
54 void RegScavenger::initRegState() { in initRegState()
79 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { in enterBasicBlock()
111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { in addRegWithSubRegs()
117 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) { in addRegWithAliases()
123 void RegScavenger::forward() { in forward()
231 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) { in getRegsUsed()
238 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { in FindUnusedReg()
251 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable()
[all …]
DPrologEpilogInserter.h33 class RegScavenger; variable
55 RegScavenger *RS;
DBranchFolding.h20 class RegScavenger; variable
93 RegScavenger *RS;
/external/llvm/lib/CodeGen/
DRegisterScavenging.cpp34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { in setRegUsed()
42 void RegScavenger::initRegState() { in initRegState()
63 void RegScavenger::enterBasicBlock(MachineBasicBlock &MBB) { in enterBasicBlock()
92 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) { in addRegUnits()
97 void RegScavenger::determineKillsAndDefs() { in determineKillsAndDefs()
144 void RegScavenger::unprocess() { in unprocess()
163 void RegScavenger::forward() { in forward()
248 bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const { in isRegUsed()
257 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { in FindUnusedReg()
268 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable()
[all …]
DShrinkWrap.cpp135 bool useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS) const;
137 const SetOfRegs &getCurrentCSRs(RegScavenger *RS) const { in getCurrentCSRs()
157 void updateSaveRestorePoints(MachineBasicBlock &MBB, RegScavenger *RS);
224 RegScavenger *RS) const { in INITIALIZE_PASS_DEPENDENCY()
273 RegScavenger *RS) { in updateSaveRestorePoints()
443 std::unique_ptr<RegScavenger> RS( in runOnMachineFunction()
444 TRI->requiresRegisterScavenging(MF) ? new RegScavenger() : nullptr); in runOnMachineFunction()
DPrologEpilogInserter.cpp51 static void doSpillCalleeSavedRegs(MachineFunction &MF, RegScavenger *RS,
57 static void doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS);
67 SpillCalleeSavedRegisters = [](MachineFunction &, RegScavenger *, in PEI()
70 ScavengeFrameVirtualRegs = [](MachineFunction &, RegScavenger *) {}; in PEI() argument
93 std::function<void(MachineFunction &MF, RegScavenger *RS,
98 std::function<void(MachineFunction &MF, RegScavenger *RS)>
103 RegScavenger *RS;
177 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr; in runOnMachineFunction()
530 static void doSpillCalleeSavedRegs(MachineFunction &Fn, RegScavenger *RS, in doSpillCalleeSavedRegs()
1157 doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS) { in doScavengeFrameVirtualRegs()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.h54 int SPAdj, RegScavenger *RS) const;
56 int SPAdj, RegScavenger *RS) const;
58 int SPAdj, RegScavenger *RS = NULL) const;
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.h93 RegScavenger *RS = nullptr) const override;
95 RegScavenger *RS = nullptr) const override;
96 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegisterInfo.h25 class RegScavenger; variable
40 RegScavenger *RS = nullptr) const override;
/external/llvm/include/llvm/Target/
DTargetFrameLowering.h25 class RegScavenger; variable
270 RegScavenger *RS = nullptr) const;
278 RegScavenger *RS = nullptr) const {
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPURegisterInfo.h75 RegScavenger *RS = NULL) const;
94 RegScavenger *RS,
/external/llvm/lib/Target/XCore/
DXCoreFrameLowering.h51 RegScavenger *RS = nullptr) const override;
54 RegScavenger *RS = nullptr) const override;
DXCoreRegisterInfo.cpp96 int Offset, RegScavenger *RS ) { in InsertFPConstInst()
164 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst()
263 RegScavenger *RS) const { in eliminateFrameIndex()
/external/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.h31 RegScavenger *RS) const override;
42 RegScavenger *RS) const override;
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.h23 class RegScavenger; variable
86 RegScavenger *RS = nullptr) const override;
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetFrameLowering.h29 class RegScavenger; variable
182 RegScavenger *RS = NULL) const {
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DRegisterScavenging.h30 class RegScavenger {
72 RegScavenger() in RegScavenger() function
/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h32 class RegScavenger {
72 RegScavenger() in RegScavenger() function
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h82 RegScavenger *RS) const override;
200 RegScavenger *RS) const;
DR600RegisterInfo.h49 RegScavenger *RS = nullptr) const override;
/external/llvm/lib/Target/X86/
DX86FrameLowering.h78 RegScavenger *RS = nullptr) const override;
114 RegScavenger *RS) const override;
/external/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.h49 RegScavenger *RS = nullptr) const override;
51 RegScavenger *RS) const override;
/external/llvm/lib/Target/BPF/
DBPFRegisterInfo.h34 RegScavenger *RS = nullptr) const override;
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsFrameLowering.h44 RegScavenger *RS) const;
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.h38 RegScavenger *RS = nullptr) const override;

123456