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Searched refs:RegTy (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp3752 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
3753 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
3761 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
3781 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
3793 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
3821 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
3834 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
3838 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
3874 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
3875 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
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/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp183 struct RegTy { struct
197 struct RegTy Reg;
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2539 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; in SelectCMP_SWAP() local
2544 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
/external/clang/lib/CodeGen/
DTargetInfo.cpp4263 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits); in classifyArgumentType() local
4264 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs); in classifyArgumentType()