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Searched refs:Rt (Results 1 – 25 of 205) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td43 // Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt
44 def : InstAlias<"memb($Rs) = $Rt",
45 (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
47 def : InstAlias<"memh($Rs) = $Rt",
48 (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
50 def : InstAlias<"memh($Rs) = $Rt.h",
51 (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
53 def : InstAlias<"memw($Rs) = $Rt",
54 (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
56 def : InstAlias<"memb($Rs) = $Rt.new",
[all …]
DHexagonInstrInfoVector.td177 : Pat <(Op Value:$Rs, I32:$Rt),
178 (MI Value:$Rs, I32:$Rt)>;
207 : Pat <(i1 (Op Value:$Rs, Value:$Rt)),
208 (MI Value:$Rs, Value:$Rt)>;
224 : Pat <(OutTy (Op InVal:$Rs, InVal:$Rt)),
225 (MI InVal:$Rs, InVal:$Rt)>;
242 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
244 [(set V2I32:$Rd, (mul V2I32:$Rs, V2I32:$Rt))]>;
248 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt),
250 [(set V2I32:$Rd, (add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)))],
[all …]
DHexagonIntrinsics.td39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
40 (MI ImmPred:$Is, I32:$Rt)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
51 : Pat <(IntID I32:$Rs, I32:$Rt),
52 (MI I32:$Rs, I32:$Rt)>;
55 : Pat <(IntID I64:$Rs, I64:$Rt),
56 (MI I64:$Rs, I64:$Rt)>;
59 : Pat <(IntID I32:$Rs, I32:$Rt),
60 (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>;
[all …]
DHexagonSystemInst.td24 bits<5> Rt;
31 let Inst{12-8} = Rt;
42 bits<5> Rt;
49 let Inst{12-8} = Rt;
54 let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in {
59 let Rt = 0, Rd = 0 in {
71 def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt),
72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
73 def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt),
74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
DHexagonAsmPrinter.cpp330 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
331 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
332 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
341 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
342 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
343 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
353 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
354 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
[all …]
DHexagonInstrInfo.td121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
129 bits<5> Rt;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
156 bits<5> Rt;
163 let Inst{20-16} = !if(OpsRev,Rt,Rs);
165 let Inst{12-8} = !if(OpsRev,Rs,Rt);
[all …]
DHexagonIntrinsicsV4.td33 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
37 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
42 // Rdd=vpmpyh(Rs,Rt)
44 // Rxx[^]=vpmpyh(Rs,Rt)
48 // Rdd=pmpyw(Rs,Rt)
50 // Rxx^=pmpyw(Rs,Rt)
53 //Rxx^=asr(Rss,Rt)
55 //Rxx^=asl(Rss,Rt)
57 //Rxx^=lsr(Rss,Rt)
59 //Rxx^=lsl(Rss,Rt)
[all …]
DHexagonInstrInfoV3.td108 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
110 (i64 DoubleRegs:$Rt))))],
116 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
118 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
121 bits<5> Rt;
127 let Inst{20-16} = !if(isMax, Rt, Rs);
128 let Inst{12-8} = !if(isMax, Rs, Rt);
223 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
224 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
265 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
[all …]
DHexagonInstrInfoV4.td131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
176 bits<5> Rt;
181 let Inst{12-8} = Rt;
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dalu64.ll5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-memop-rs-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
36 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1
37 // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1
38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
[all …]
Dcond-rd-memop-immediate-8192-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
35 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
36 // STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
37 // STR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
38 "Strb" // STRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
[all …]
Dcond-rd-memop-rs-shift-amount-1to31-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
36 // STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
37 // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
38 "Strb" // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
[all …]
Dcond-rd-memop-immediate-512-a32.json29 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
30 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
31 // LDRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
32 "Ldrsh", // LDRSH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1
33 // LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1
34 // LDRSH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
35 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1
36 // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1
37 // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
38 "Strh" // STRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
[all …]
/external/eigen/Eigen/src/Geometry/
DUmeyama.h134 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); variable
143 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();
151 Rt.col(m).head(m) = dst_mean;
152 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean;
153 Rt.block(0,0,m,m) *= c;
157 Rt.col(m).head(m) = dst_mean;
158 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean;
161 return Rt;
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td977 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
978 opc, ".w\t$Rt, $addr",
979 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
980 bits<4> Rt;
988 let Inst{15-12} = Rt;
993 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
994 opc, "\t$Rt, $addr",
995 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
996 bits<4> Rt;
1005 let Inst{15-12} = Rt;
[all …]
DARMInstrInfo.td1730 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1731 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1732 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1733 bits<4> Rt;
1737 let Inst{15-12} = Rt;
1740 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1741 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1742 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1743 bits<4> Rt;
1748 let Inst{15-12} = Rt;
[all …]
/external/capstone/arch/Mips/
DMipsDisassembler.c537 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch_4() local
541 if (Rs >= Rt) { in DecodeAddiGroupBranch_4()
544 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch_4()
553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeAddiGroupBranch_4()
573 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch_4() local
577 if (Rs >= Rt) { in DecodeDaddiGroupBranch_4()
580 } else if (Rs != 0 && Rs < Rt) { in DecodeDaddiGroupBranch_4()
589 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeDaddiGroupBranch_4()
610 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch_4() local
614 if (Rt == 0) in DecodeBlezlGroupBranch_4()
[all …]
/external/capstone/arch/AArch64/
DAArch64Disassembler.c943 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
952 MCOperand_CreateImm0(Inst, Rt); in DecodeUnsignedLdStInstruction()
962 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
969 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
973 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
977 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
981 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
985 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
989 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1007 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
[all …]
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp603 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
607 if (Rs >= Rt) { in DecodeAddiGroupBranch()
610 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
621 Rt))); in DecodeAddiGroupBranch()
631 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
635 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
638 Rt))); in DecodePOP35GroupBranchMMR6()
641 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
646 Rt))); in DecodePOP35GroupBranchMMR6()
650 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td877 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
878 opc, ".w\t$Rt, $addr",
879 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
880 bits<4> Rt;
888 let Inst{15-12} = Rt;
891 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
892 opc, "\t$Rt, $addr",
893 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
894 bits<4> Rt;
903 let Inst{15-12} = Rt;
[all …]
DARMInstrInfo.td1408 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1409 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1410 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1411 bits<4> Rt;
1415 let Inst{15-12} = Rt;
1418 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1419 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1420 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1421 bits<4> Rt;
1426 let Inst{15-12} = Rt;
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp207 MCOperand Rs, Rt; in getCompoundInsn() local
217 Rt = L.getOperand(0); in getCompoundInsn()
222 CompoundInsn->addOperand(Rt); in getCompoundInsn()
228 Rt = L.getOperand(0); in getCompoundInsn()
234 CompoundInsn->addOperand(Rt); in getCompoundInsn()
243 Rt = L.getOperand(2); in getCompoundInsn()
249 CompoundInsn->addOperand(Rt); in getCompoundInsn()
256 Rt = L.getOperand(2); in getCompoundInsn()
262 CompoundInsn->addOperand(Rt); in getCompoundInsn()
269 Rt = L.getOperand(2); in getCompoundInsn()
[all …]
/external/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRsRt() local
213 Opcode |= Rt << 16; in emitRsRt()
221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16() local
225 Opcode |= Rt << 16; in emitRtRsImm16()
236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16Rel() local
249 Opcode |= Rt << 16; in emitRtRsImm16Rel()
272 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRtSa() local
274 Opcode |= Rt << 16; in emitRdRtSa()
286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRsRt() local
289 Opcode |= Rt << 16; in emitRdRsRt()
[all …]
/external/capstone/arch/ARM/
DARMDisassembler.c1519 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1545 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1578 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1668 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeAddrMode3Instruction() local
1677 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
1689 if (Rt & 0x1) S = MCDisassembler_SoftFail; in DecodeAddrMode3Instruction()
1701 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1713 if (Rt == 15) in DecodeAddrMode3Instruction()
1715 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1730 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
[all …]

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