| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 68 SP::G0, SP::G1, SP::G2, SP::G3,
69 SP::G4, SP::G5, SP::G6, SP::G7,
70 SP::O0, SP::O1, SP::O2, SP::O3,
71 SP::O4, SP::O5, SP::O6, SP::O7,
72 SP::L0, SP::L1, SP::L2, SP::L3,
73 SP::L4, SP::L5, SP::L6, SP::L7,
74 SP::I0, SP::I1, SP::I2, SP::I3,
75 SP::I4, SP::I5, SP::I6, SP::I7 };
78 SP::F0, SP::F1, SP::F2, SP::F3,
79 SP::F4, SP::F5, SP::F6, SP::F7,
[all …]
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| /external/libunwind/doc/ |
| D | unw_create_addr_space.tex | 55 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{unw\_word\_t} \Var{ip}, \Type{unw\_proc\_info…
56 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{int} \Var{need\_unwind\_info}, \Type{void~*}a…
58 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{unw\_proc\_info\_t~*}pip, \Type{void~*}\Var{a…
60 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{unw\_word\_t~*}\Var{dilap}, \Type{void~*}\Var…
62 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{unw\_word\_t} \Var{addr}, \Type{unw\_word\_t~…
63 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{int} \Var{write}, \Type{void~*}\Var{arg});\\
65 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{unw\_regnum\_t} \Var{regnum}, \Type{unw\_word…
66 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{int} \Var{write}, \Type{void~*}\Var{arg});\\
68 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{unw\_regnum\_t} \Var{regnum}, \Type{unw\_fpre…
69 \SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\SP\Type{int} \Var{write}, \Type{void~*}\Var{arg});\\
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | FPMover.cpp | 63 SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14, in getDoubleRegPair()
64 SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30 in getDoubleRegPair()
67 SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15, in getDoubleRegPair()
68 SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31 in getDoubleRegPair()
71 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, in getDoubleRegPair()
72 SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15 in getDoubleRegPair()
90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || in runOnMachineBasicBlock()
91 MI->getOpcode() == SP::FpNEGD) { in runOnMachineBasicBlock()
95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) { in runOnMachineBasicBlock()
106 if (MI->getOpcode() == SP::FpMOVD) in runOnMachineBasicBlock()
[all …]
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| D | SparcRegisterInfo.cpp | 33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) { in SparcRegisterInfo()
45 Reserved.set(SP::G1); in getReservedRegs()
46 Reserved.set(SP::G2); in getReservedRegs()
47 Reserved.set(SP::G3); in getReservedRegs()
48 Reserved.set(SP::G4); in getReservedRegs()
49 Reserved.set(SP::O6); in getReservedRegs()
50 Reserved.set(SP::I6); in getReservedRegs()
51 Reserved.set(SP::I7); in getReservedRegs()
52 Reserved.set(SP::G0); in getReservedRegs()
53 Reserved.set(SP::G5); in getReservedRegs()
[all …]
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| D | SparcInstrInfo.cpp | 31 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), in SparcInstrInfo()
42 if (MI->getOpcode() == SP::LDri || in isLoadFromStackSlot()
43 MI->getOpcode() == SP::LDFri || in isLoadFromStackSlot()
44 MI->getOpcode() == SP::LDDFri) { in isLoadFromStackSlot()
61 if (MI->getOpcode() == SP::STri || in isStoreToStackSlot()
62 MI->getOpcode() == SP::STFri || in isStoreToStackSlot()
63 MI->getOpcode() == SP::STDFri) { in isStoreToStackSlot()
140 if (I->getOpcode() == SP::BA) { in AnalyzeBranch()
167 if (Opcode != SP::BCOND && Opcode != SP::FBCOND) in AnalyzeBranch()
196 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) in AnalyzeBranch()
[all …]
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| D | SparcFrameLowering.cpp | 55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) in emitPrologue()
56 .addReg(SP::O6).addImm(NumBytes); in emitPrologue()
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); in emitPrologue()
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitPrologue()
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); in emitPrologue()
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) in emitPrologue()
66 .addReg(SP::O6).addReg(SP::G1); in emitPrologue()
76 assert(MBBI->getOpcode() == SP::RETL && in emitEpilogue()
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
79 .addReg(SP::G0); in emitEpilogue()
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| /external/boringssl/src/ssl/test/runner/curve25519/ |
| D | ladderstep_amd64.s | 41 MOVQ SI,0(SP)
42 MOVQ DX,8(SP)
43 MOVQ CX,16(SP)
44 MOVQ R8,24(SP)
45 MOVQ R9,32(SP)
46 MOVQ AX,40(SP)
47 MOVQ R10,48(SP)
48 MOVQ R11,56(SP)
49 MOVQ R12,64(SP)
50 MOVQ R13,72(SP)
[all …]
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| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| D | SparcInstPrinter.cpp | 30 using namespace SP;
59 case SP::JMPLrr: in printSparcAliasInstr()
60 case SP::JMPLri: { in printSparcAliasInstr()
67 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
72 case SP::I7: O << "\tret"; return true; in printSparcAliasInstr()
73 case SP::O7: O << "\tretl"; return true; in printSparcAliasInstr()
78 case SP::O7: // call $addr in printSparcAliasInstr()
83 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
84 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
88 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
53 .addReg(SP::O6).addImm(NumBytes); in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
67 .addReg(SP::G1).addImm(LO10(NumBytes)); in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
80 .addReg(SP::G1).addImm(LOX10(NumBytes)); in emitSPAdjustment()
[all …]
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| D | SparcRegisterInfo.cpp | 37 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {} in SparcRegisterInfo()
59 Reserved.set(SP::G1); in getReservedRegs()
63 Reserved.set(SP::G2); in getReservedRegs()
64 Reserved.set(SP::G3); in getReservedRegs()
65 Reserved.set(SP::G4); in getReservedRegs()
69 Reserved.set(SP::G5); in getReservedRegs()
71 Reserved.set(SP::O6); in getReservedRegs()
72 Reserved.set(SP::I6); in getReservedRegs()
73 Reserved.set(SP::I7); in getReservedRegs()
74 Reserved.set(SP::G0); in getReservedRegs()
[all …]
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| D | SparcInstrInfo.cpp | 36 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), in SparcInstrInfo()
46 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
47 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || in isLoadFromStackSlot()
48 MI.getOpcode() == SP::LDQFri) { in isLoadFromStackSlot()
65 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || in isStoreToStackSlot()
66 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || in isStoreToStackSlot()
67 MI.getOpcode() == SP::STQFri) { in isStoreToStackSlot()
144 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode()
147 return Opc == SP::FBCOND || Opc == SP::BCOND; in isCondBranchOpcode()
151 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
[all …]
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| D | DelaySlotFiller.cpp | 120 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
121 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
129 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
130 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
131 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
149 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
159 TII->get(SP::UNIMP)).addImm(structSize); in runOnMachineBasicBlock()
181 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
184 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
188 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
[all …]
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| D | LeonPasses.cpp | 52 for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) { in getUnusedFPRegister()
89 if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) { in runOnMachineFunction()
91 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
99 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
146 if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) { in runOnMachineFunction()
194 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
199 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
204 BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD)) in runOnMachineFunction()
258 if (Opcode == SP::FMULS && MI.getNumOperands() == 3) { in runOnMachineFunction()
305 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
[all …]
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| D | SparcAsmPrinter.cpp | 113 CallInst.setOpcode(SP::CALL); in EmitCall()
123 SETHIInst.setOpcode(SP::SETHIi); in EmitSETHI()
144 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); in EmitOR()
150 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI); in EmitADD()
156 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI); in EmitSHL()
180 assert(MO.getReg() != SP::O7 && in LowerGETPCXAndEmitMCInsts()
216 MCOperand RegO7 = MCOperand::createReg(SP::O7); in LowerGETPCXAndEmitMCInsts()
230 MCOperand RegO7 = MCOperand::createReg(SP::O7); in LowerGETPCXAndEmitMCInsts()
264 case SP::GETPCX: in EmitInstruction()
282 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; in EmitFunctionBodyStart()
[all …]
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| D | SparcISelLowering.cpp | 57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_Split_64()
85 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_Ret_Split_64()
119 Reg = SP::I0 + Offset/8; in CC_Sparc64_Full()
122 Reg = SP::D0 + Offset/8; in CC_Sparc64_Full()
125 Reg = SP::F1 + Offset/4; in CC_Sparc64_Full()
128 Reg = SP::Q0 + Offset/16; in CC_Sparc64_Full()
157 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, in CC_Sparc64_Half()
164 unsigned Reg = SP::I0 + Offset/8; in CC_Sparc64_Half()
187 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7, in toCallerWindow()
189 if (Reg >= SP::I0 && Reg <= SP::I7) in toCallerWindow()
[all …]
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| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 23 ; O32: addiu [[SP:\$sp]], $sp, -8
24 ; N32: addiu [[SP:\$sp]], $sp, -64
25 ; N64: daddiu [[SP:\$sp]], $sp, -64
28 ; O32-DAG: sw $7, 20([[SP]])
29 ; O32-DAG: sw $6, 16([[SP]])
30 ; O32-DAG: sw $5, 12([[SP]])
32 ; NEW-DAG: sd $11, 56([[SP]])
33 ; NEW-DAG: sd $10, 48([[SP]])
34 ; NEW-DAG: sd $9, 40([[SP]])
35 ; NEW-DAG: sd $8, 32([[SP]])
[all …]
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| /external/icu/icu4c/source/test/testdata/ |
| D | LineBreakTest.txt | 30 × 0023 × 0020 ÷ 0023 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] NUMBER SIGN (AL) ÷ …
32 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] NUMBER SIG…
34 × 0023 × 0020 ÷ 2014 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] EM DASH (B2) ÷ [0.3]
36 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] EM DASH (B…
38 × 0023 × 0020 ÷ 0009 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] <CHARACTER TABULATI…
40 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] <CHARACTER…
42 × 0023 × 0020 ÷ 00B4 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] ACUTE ACCENT (BB) ÷…
44 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] ACUTE ACCE…
46 × 0023 × 0020 × 000B ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) × [6.0] <LINE TABULATION> (B…
48 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) × [6.0] <LINE TABUL…
[all …]
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| /external/valgrind/coregrind/m_dispatch/ |
| D | dispatch-s390x-linux.S | 51 #undef SP
52 #define SP S390_REGNO_STACK_POINTER macro
58 #define S390_LOC_SAVED_FPC_V S390_OFFSET_SAVED_FPC_V(SP)
61 #define S390_LOC_SAVED_R2 S390_OFFSET_SAVED_R2(SP)
90 stmg %r6,%r15,48(SP)
93 aghi SP,-S390_INNERLOOP_FRAME_SIZE
96 std %f8,160+0(SP)
97 std %f9,160+8(SP)
98 std %f10,160+16(SP)
99 std %f11,160+24(SP)
[all …]
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_cos_sin_mod.s | 40 STMFD SP!, {R4-R12, R14}
51 SUB R10, SP, #516
52 SUB SP, SP, #516
64 STMFD SP!, {R0-R3}
218 LDR R1, [SP, #4]
220 LDR R4, [SP, #8]
221 LDR R0, [SP, #8]
222 ADD R1, SP, #16
231 LDR R5, [SP, #12]
243 LDR R3, [SP]
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll | 10 define void @foo(double %vfp0, ; --> D0, NSAA=SP
11 double %vfp1, ; --> D1, NSAA=SP
12 double %vfp2, ; --> D2, NSAA=SP
13 double %vfp3, ; --> D3, NSAA=SP
14 double %vfp4, ; --> D4, NSAA=SP
15 double %vfp5, ; --> D5, NSAA=SP
16 double %vfp6, ; --> D6, NSAA=SP
17 double %vfp7, ; --> D7, NSAA=SP
18 double %vfp8, ; --> SP, NSAA=SP+8 (!)
19 i32 %p0, ; --> R0, NSAA=SP+8
[all …]
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| D | 2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll | 8 define void @foo(double %vfp0, ; --> D0, NSAA=SP
9 double %vfp1, ; --> D1, NSAA=SP
10 double %vfp2, ; --> D2, NSAA=SP
11 double %vfp3, ; --> D3, NSAA=SP
12 double %vfp4, ; --> D4, NSAA=SP
13 double %vfp5, ; --> D5, NSAA=SP
14 double %vfp6, ; --> D6, NSAA=SP
15 double %vfp7, ; --> D7, NSAA=SP
16 double %vfp8, ; --> SP, NSAA=SP+8 (!)
17 i32 %p0, ; --> R0, NSAA=SP+8
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | arm-load-store-multiple-deprecated.s | 14 @ CHECK: warning: use of SP or PC in the list is deprecated
18 @ CHECK: warning: use of SP or PC in the list is deprecated
22 @ CHECK: warning: use of SP or PC in the list is deprecated
26 @ CHECK: warning: use of SP or PC in the list is deprecated
30 @ CHECK: warning: use of SP or PC in the list is deprecated
34 @ CHECK: warning: use of SP or PC in the list is deprecated
42 @ CHECK: warning: use of SP or PC in the list is deprecated
46 @ CHECK: warning: use of SP or PC in the list is deprecated
50 @ CHECK: warning: use of SP or PC in the list is deprecated
54 @ CHECK: warning: use of SP or PC in the list is deprecated
[all …]
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| /external/llvm/lib/IR/ |
| D | DebugInfo.cpp | 73 else if (auto *SP = dyn_cast<DISubprogram>(Entity)) in processModule() local
74 processSubprogram(SP); in processModule()
82 if (auto *SP = cast_or_null<DISubprogram>(F.getSubprogram())) in processModule() local
83 processSubprogram(SP); in processModule()
107 else if (auto *SP = dyn_cast<DISubprogram>(D)) in processType() local
108 processSubprogram(SP); in processType()
128 if (auto *SP = dyn_cast<DISubprogram>(Scope)) { in processScope() local
129 processSubprogram(SP); in processScope()
143 void DebugInfoFinder::processSubprogram(DISubprogram *SP) { in processSubprogram() argument
144 if (!addSubprogram(SP)) in processSubprogram()
[all …]
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| /external/llvm/test/CodeGen/WebAssembly/ |
| D | byval.ll | 27 ; Subtract 16 from SP (SP is 16-byte aligned)
32 ; Ensure SP is stored back before the call
34 ; CHECK-NEXT: tee_local $push[[L11:.+]]=, $[[SP:.+]]=, $pop[[L12]]{{$}}
35 ; Copy the SmallStruct argument to the stack (SP+12, original SP-4)
40 ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}}
46 ; CHECK-NEXT: i32.add $push[[L8:.+]]=, $[[SP]], $pop[[L6]]
55 ; Don't check the entire SP sequence, just enough to get the alignment.
59 ; CHECK-NEXT: tee_local $push[[L11:.+]]=, $[[SP:.+]]=, $pop[[L12]]{{$}}
60 ; Copy the SmallStruct argument to the stack (SP+8, original SP-8)
65 ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}}
[all …]
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| /external/llvm/test/CodeGen/NVPTX/ |
| D | local-stack-frame.ll | 7 ; PTX32: cvta.local.u32 %SP, %SPL;
9 ; PTX32: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
11 ; PTX64: cvta.local.u64 %SP, %SPL;
13 ; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
21 ; PTX32: cvta.local.u32 %SP, %SPL;
26 ; PTX64: cvta.local.u64 %SP, %SPL;
43 ; PTX32-NOT: cvta.local.u32 %SP, %SPL;
48 ; PTX64-NOT: cvta.local.u64 %SP, %SPL;
60 ; PTX32: cvta.local.u32 %SP, %SPL;
61 ; PTX32: add.u32 {{%r[0-9]+}}, %SP, 0;
[all …]
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