| /external/vixl/test/aarch32/config/ |
| D | cond-dt-drt-drd-drn-drm-float.json | 35 "Vceq", // VCEQ{<c>}{<q>}.<dt> {<Dd>}, <Dn>, <Dm> ; A2
36 // VCEQ{<c>}{<q>}.<dt> {<Dd>}, <Dn>, <Dm> ; T2
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vicmp.ll | 4 ; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)
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| D | vfcmp.ll | 5 ; une is implemented with VCEQ/VMVN
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| /external/llvm/test/CodeGen/ARM/ |
| D | vicmp.ll | 4 ; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)
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| D | vfcmp.ll | 5 ; une is implemented with VCEQ/VMVN
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| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 1343 VCEQ/VCEQQ output:
1344 VCEQ/VCEQQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, 0, }
1345 VCEQ/VCEQQ:1:result_uint16x4 [] = { 0, 0, ffff, 0, }
1346 VCEQ/VCEQQ:2:result_uint32x2 [] = { ffffffff, 0, }
1347 VCEQ/VCEQQ:3:result_uint8x8 [] = { 0, 0, 0, ff, 0, 0, 0, 0, }
1348 VCEQ/VCEQQ:4:result_uint16x4 [] = { 0, 0, ffff, 0, }
1349 VCEQ/VCEQQ:5:result_uint32x2 [] = { 0, ffffffff, }
1350 VCEQ/VCEQQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, 0, 0, 0, }
1351 VCEQ/VCEQQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, 0, }
1352 VCEQ/VCEQQ:8:result_uint32x4 [] = { 0, 0, ffffffff, 0, }
[all …]
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| D | ref-rvct-neon.txt | 1435 VCEQ/VCEQQ output:
1436 VCEQ/VCEQQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, 0, }
1437 VCEQ/VCEQQ:1:result_uint16x4 [] = { 0, 0, ffff, 0, }
1438 VCEQ/VCEQQ:2:result_uint32x2 [] = { ffffffff, 0, }
1439 VCEQ/VCEQQ:3:result_uint8x8 [] = { 0, 0, 0, ff, 0, 0, 0, 0, }
1440 VCEQ/VCEQQ:4:result_uint16x4 [] = { 0, 0, ffff, 0, }
1441 VCEQ/VCEQQ:5:result_uint32x2 [] = { 0, ffffffff, }
1442 VCEQ/VCEQQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, 0, 0, 0, }
1443 VCEQ/VCEQQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, 0, }
1444 VCEQ/VCEQQ:8:result_uint32x4 [] = { 0, 0, ffffffff, 0, }
[all …]
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| D | ref-rvct-all.txt | 1435 VCEQ/VCEQQ output:
1436 VCEQ/VCEQQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, 0, }
1437 VCEQ/VCEQQ:1:result_uint16x4 [] = { 0, 0, ffff, 0, }
1438 VCEQ/VCEQQ:2:result_uint32x2 [] = { ffffffff, 0, }
1439 VCEQ/VCEQQ:3:result_uint8x8 [] = { 0, 0, 0, ff, 0, 0, 0, 0, }
1440 VCEQ/VCEQQ:4:result_uint16x4 [] = { 0, 0, ffff, 0, }
1441 VCEQ/VCEQQ:5:result_uint32x2 [] = { 0, ffffffff, }
1442 VCEQ/VCEQQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, 0, 0, 0, }
1443 VCEQ/VCEQQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, 0, }
1444 VCEQ/VCEQQ:8:result_uint32x4 [] = { 0, 0, ffffffff, 0, }
[all …]
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| D | expected_input4gcc-nofp16.txt | 1252 VCEQ/VCEQQ output:
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| D | expected_input4gcc.txt | 1344 VCEQ/VCEQQ output:
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 97 VCEQ, // Vector compare equal. enumerator
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| D | ARMISelLowering.cpp | 867 case ARMISD::VCEQ: return "ARMISD::VCEQ"; in getTargetNodeName()
3449 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; in LowerVSETCC()
3486 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; in LowerVSETCC()
3498 if (Opc == ARMISD::VCEQ) { in LowerVSETCC()
3538 case ARMISD::VCEQ: in LowerVSETCC()
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| D | ARMInstrNEON.td | 50 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
3662 // VCEQ : Vector Compare Equal
3663 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 169 VCEQ, enumerator
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| D | MipsISelLowering.cpp | 200 case MipsISD::VCEQ: return "MipsISD::VCEQ"; in getTargetNodeName()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 96 VCEQ, // Vector compare equal. enumerator
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| D | ARMScheduleSwift.td | 555 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
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| D | ARMISelLowering.cpp | 1171 case ARMISD::VCEQ: return "ARMISD::VCEQ"; in getTargetNodeName()
4896 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; in LowerVSETCC()
4933 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; in LowerVSETCC()
4945 if (Opc == ARMISD::VCEQ) { in LowerVSETCC()
4985 case ARMISD::VCEQ: in LowerVSETCC()
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| D | ARMScheduleA9.td | 2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
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| D | ARMInstrNEON.td | 495 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
4711 // VCEQ : Vector Compare Equal
4712 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4284 VCEQ, enumerator
4319 case VCEQ: in EncodeNeonBinOp()
4553 emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2)); in vceq()
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| /external/v8/src/s390/ |
| D | constants-s390.h | 545 V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 551 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
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| /external/valgrind/none/tests/arm/ |
| D | neon128.stdout.exp | 1356 ---- VCEQ ----
1812 ---- VCEQ #0 ----
4004 ---- VCEQ (fp) ----
4054 ---- VCEQ (fp) #0 ----
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| D | neon64.stdout.exp | 1602 ---- VCEQ ----
3056 ---- VCEQ #0 ----
6085 ---- VCEQ (fp) ----
6184 ---- VCEQ (fp) #0 ----
|