Home
last modified time | relevance | path

Searched refs:fcvtzs (Results 1 – 25 of 53) sorted by relevance

123

/external/llvm/test/CodeGen/AArch64/
Dcomplex-fp-to-int.ll6 ; CHECK: fcvtzs.2d v0, [[VAL64]]
23 ; CHECK: fcvtzs.2s v0, v0
31 ; CHECK: fcvtzs.2s v0, v0
39 ; CHECK: fcvtzs.2s v0, v0
47 ; CHECK: fcvtzs.2s v0, v0
55 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
73 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
82 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
91 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
109 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
[all …]
Dfcvt_combine.ll5 ; CHECK: fcvtzs.2s v0, v0, #4
15 ; CHECK: fcvtzs.4s v0, v0, #3
25 ; CHECK: fcvtzs.2d v0, v0, #5
36 ; CHECK: fcvtzs.2d v0, v0
48 ; CHECK: fcvtzs.2s v0, v0, #4
61 ; CHECK: fcvtzs.2d v0, v0
127 ; CHECK: fcvtzs.2s v0, v0
138 ; CHECK: fcvtzs.2s v0, v0
148 ; CHECK: fcvtzs.2s v0, v0, #32
157 ; CHECK: fcvtzs.4s v0, v0, #2
Darm64-convert-v4f64.ll6 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
7 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
18 ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d
19 ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d
20 ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d
21 ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d
Dfcvt-fixed.ll15 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7
20 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32
25 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7
30 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64
35 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7
40 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32
45 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7
50 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64
Darm64-cvt.ll328 ;CHECK: fcvtzs w0, s0
330 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %A)
336 ;CHECK: fcvtzs x0, s0
338 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)
344 ;CHECK: fcvtzs w0, d0
346 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double %A)
352 ;CHECK: fcvtzs x0, d0
354 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %A)
358 declare i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float) nounwind readnone
359 declare i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float) nounwind readnone
[all …]
Dfcvt-int.ll9 ; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}}
24 ; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}}
39 ; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}}
54 ; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}}
Darm64-vcvt_su32_f32.ll5 ; CHECK: fcvtzs.2s v0, v0
21 ; CHECK: fcvtzs.4s v0, v0
Dround-conv.ll164 ; CHECK: fcvtzs w0, s0
174 ; CHECK: fcvtzs x0, s0
184 ; CHECK: fcvtzs w0, d0
194 ; CHECK: fcvtzs x0, d0
Darm64-vcvt.ll254 ;CHECK: fcvtzs.2s v0, v0
263 ;CHECK: fcvtzs.4s v0, v0
272 ;CHECK: fcvtzs.2d v0, v0
547 ;CHECK: fcvtzs.2s v0, v0, #1
556 ;CHECK: fcvtzs.4s v0, v0, #1
565 ;CHECK: fcvtzs.2d v0, v0, #1
Darm64-fast-isel-noconvert.ll32 ; CHECK: fcvtzs.2d v0, v0
Dfp16-v8-instructions.ll374 ; CHECK-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]]
376 ; CHECK-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]]
388 ; CHECK-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]]
390 ; CHECK-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]]
Dfp16-v4-instructions.ll232 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
242 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
252 ; NOTE: fcvtzs selected here because the xtn shaves the sign bit
253 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s57 fcvtzs h21, h12, #1
58 fcvtzs s21, s12, #1
59 fcvtzs d21, d12, #1
194 fcvtzs h12, h13
195 fcvtzs s12, s13
196 fcvtzs d21, d14
Darm64-fp-encoding.s398 fcvtzs w1, h2
399 fcvtzs w1, h2, #1
400 fcvtzs w1, s2
401 fcvtzs w1, s2, #1
402 fcvtzs w1, d2
403 fcvtzs w1, d2, #1
404 fcvtzs x1, h2
405 fcvtzs x1, h2, #1
406 fcvtzs x1, s2
407 fcvtzs x1, s2, #1
[all …]
Dneon-simd-shift.s428 fcvtzs v0.4h, v1.4h, #3
429 fcvtzs v0.8h, v1.8h, #3
430 fcvtzs v0.2s, v1.2s, #3
431 fcvtzs v0.4s, v1.4s, #3
432 fcvtzs v0.2d, v1.2d, #3
Dneon-simd-misc.s621 fcvtzs v4.4h, v0.4h
622 fcvtzs v6.8h, v8.8h
623 fcvtzs v6.4s, v8.4s
624 fcvtzs v6.2d, v8.2d
625 fcvtzs v4.2s, v0.2s
Dfullfp16-neon-neg.s226 fcvtzs h21, h12, #1
246 fcvtzs h12, h13
354 fcvtzs v4.4h, v0.4h
356 fcvtzs v6.8h, v8.8h
Dbasic-a64-instructions.s1953 fcvtzs w3, s5, #1
1954 fcvtzs wzr, s20, #13
1955 fcvtzs w19, s0, #32
1960 fcvtzs x3, s5, #1
1961 fcvtzs x12, s30, #45
1962 fcvtzs x19, s0, #64
1967 fcvtzs w3, d5, #1
1968 fcvtzs wzr, d20, #13
1969 fcvtzs w19, d0, #32
1974 fcvtzs x3, d5, #1
[all …]
Darm64-advsimd.s900 fcvtzs.2s v0, v0
901 fcvtzs.4s v0, v0
902 fcvtzs.2d v0, v0
903 fcvtzs s0, s0
904 fcvtzs d0, d0 define
906 ; CHECK: fcvtzs.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x0e]
907 ; CHECK: fcvtzs.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x4e]
908 ; CHECK: fcvtzs.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x4e]
909 ; CHECK: fcvtzs s0, s0 ; encoding: [0x00,0xb8,0xa1,0x5e]
910 ; CHECK: fcvtzs d0, d0 ; encoding: [0x00,0xb8,0xe1,0x5e]
[all …]
Dbasic-a64-diagnostics.s1669 fcvtzs w13, s31, #0
1670 fcvtzs w19, s20, #33
1671 fcvtzs wsp, s19, #14
1682 fcvtzs x13, s31, #0
1683 fcvtzs x19, s20, #65
1684 fcvtzs sp, s19, #14
Dneon-diagnostics.s2068 fcvtzs v0.2s, v1.2d, #3
2069 fcvtzs v0.4s, v1.4h, #3
2070 fcvtzs v0.2d, v1.2s, #3
5921 fcvtzs v0.16b, v31.16b
5922 fcvtzs v2.8h, v4.8h
5923 fcvtzs v1.8b, v9.8b
5924 fcvtzs v13.4h, v21.4h
6277 fcvtzs s21, s12, #0
6278 fcvtzs d21, d12, #65
6279 fcvtzs s21, d12, #1
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs10 0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1
11 0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1
31 0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13
32 0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14
Dneon-simd-shift.s.cs146 0x20,0xfc,0x3d,0x0f = fcvtzs v0.2s, v1.2s, #3
147 0x20,0xfc,0x3d,0x4f = fcvtzs v0.4s, v1.4s, #3
148 0x20,0xfc,0x7d,0x4f = fcvtzs v0.2d, v1.2d, #3
Dneon-simd-misc.s.cs183 0x06,0xb9,0xa1,0x4e = fcvtzs v6.4s, v8.4s
184 0x06,0xb9,0xe1,0x4e = fcvtzs v6.2d, v8.2d
185 0x04,0xb8,0xa1,0x0e = fcvtzs v4.2s, v0.2s
Dbasic-a64-instructions.s.cs757 0xa3,0xfc,0x18,0x1e = fcvtzs w3, s5, #1
758 0x9f,0xce,0x18,0x1e = fcvtzs wzr, s20, #13
759 0x13,0x80,0x18,0x1e = fcvtzs w19, s0, #32
760 0xa3,0xfc,0x18,0x9e = fcvtzs x3, s5, #1
761 0xcc,0x4f,0x18,0x9e = fcvtzs x12, s30, #45
762 0x13,0x00,0x18,0x9e = fcvtzs x19, s0, #64
763 0xa3,0xfc,0x58,0x1e = fcvtzs w3, d5, #1
764 0x9f,0xce,0x58,0x1e = fcvtzs wzr, d20, #13
765 0x13,0x80,0x58,0x1e = fcvtzs w19, d0, #32
766 0xa3,0xfc,0x58,0x9e = fcvtzs x3, d5, #1
[all …]

123