/external/mesa3d/src/gallium/drivers/r600/ |
D | evergreen_hw_context.c | 49 dst_offset += rdst->gpu_address; in evergreen_dma_copy_buffer() 50 src_offset += rsrc->gpu_address; in evergreen_dma_copy_buffer() 101 offset += r600_resource(dst)->gpu_address; in evergreen_cp_dma_clear_buffer()
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D | evergreen_state.c | 628 va = tmp->resource.gpu_address + offset; in texture_buffer_sampler_view() 650 if (tmp->resource.gpu_address) in texture_buffer_sampler_view() 793 va = tmp->resource.gpu_address; in evergreen_create_sampler_view_custom() 954 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8; in evergreen_init_color_surface_rat() 1143 base_offset = rtex->resource.gpu_address; in evergreen_init_color_surface() 1179 offset = rtex->resource.gpu_address; in evergreen_init_depth_surface() 1231 stencil_offset += rtex->resource.gpu_address; in evergreen_init_depth_surface() 1247 uint64_t va = rtex->htile_buffer->gpu_address; in evergreen_init_depth_surface() 1808 va = rbuffer->gpu_address + vb->buffer_offset; in evergreen_emit_vertex_buffers() 1868 va = rbuffer->gpu_address + cb->buffer_offset; in evergreen_emit_constant_buffers() [all …]
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D | r600_hw_context.c | 406 va = buf->gpu_address + offset; in r600_emit_pfp_sync_me() 456 dst_offset += r600_resource(dst)->gpu_address; in r600_cp_dma_copy_buffer() 457 src_offset += r600_resource(src)->gpu_address; in r600_cp_dma_copy_buffer()
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D | r600_uvd.c | 125 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address( in r600_video_buffer_create()
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D | r600_state_common.c | 388 if (view->tex_resource->gpu_address && in r600_sampler_view_destroy() 1879 uint64_t va = r600_resource(info.indirect)->gpu_address; in r600_draw_vbo() 1912 uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset; in r600_draw_vbo() 1950 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset; in r600_draw_vbo() 2835 uint64_t va = rbuffer->gpu_address + offset; in r600_invalidate_buffer()
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D | evergreen_compute.c | 571 va = shader->code_bo->gpu_address + state->pc; in evergreen_emit_cs_shader()
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_compute.c | 212 va = r600_resource(resources[i])->gpu_address; in si_set_global_binding() 259 bc_va = sctx->border_color_buffer->gpu_address; in si_initialize_compute() 300 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in si_setup_compute_scratch_buffer() 375 shader_va = shader->bo->gpu_address + offset; in si_switch_compute_shader() 413 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in setup_scratch_rsrc_user_sgprs() 505 dispatch_va = dispatch_buf->gpu_address + dispatch_offset; in si_setup_user_sgprs_co_v2() 561 kernel_args_va = input_buffer->gpu_address + kernel_args_offset; in si_upload_compute_input() 604 uint64_t base_va = r600_resource(info->indirect)->gpu_address; in si_setup_tgsi_grid() 653 uint64_t base_va = r600_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
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D | si_dma.c | 50 dst_offset += rdst->gpu_address; in si_dma_copy_buffer() 51 src_offset += rsrc->gpu_address; in si_dma_copy_buffer() 102 offset += rdst->gpu_address; in si_dma_clear_buffer() 188 base += rtiled->resource.gpu_address; in si_dma_copy_tile() 189 addr += rlinear->resource.gpu_address; in si_dma_copy_tile()
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D | si_descriptors.c | 145 va = (*out_buf)->gpu_address + *out_offset; in si_ce_upload() 166 uint64_t va = buffer->gpu_address + desc->buffer_offset; in si_ce_reinitialize_descriptors() 360 uint64_t va = buf->gpu_address + offset; in si_set_buf_desc_address() 391 va = tex->resource.gpu_address + base_level_info->offset; in si_set_mutable_tex_desc_fields() 406 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + in si_set_mutable_tex_desc_fields() 411 state[7] = tex->htile_buffer->gpu_address >> 8; in si_set_mutable_tex_desc_fields() 913 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size); in si_get_buffer_from_descriptors() 914 *offset = va - res->gpu_address; in si_get_buffer_from_descriptors() 991 va = rbuffer->gpu_address + offset; in si_upload_vertex_buffer_descriptors() 1105 va = r600_resource(buffer)->gpu_address + buffer_offset; in si_set_constant_buffer() [all …]
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D | si_cp_dma.c | 232 uint64_t va = rdst->gpu_address + offset; in si_clear_buffer() 293 va = sctx->scratch_buffer->gpu_address; in si_cp_dma_realign_engine() 326 dst_offset += r600_resource(dst)->gpu_address; in si_copy_buffer() 327 src_offset += r600_resource(src)->gpu_address; in si_copy_buffer()
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D | cik_sdma.c | 49 dst_offset += rdst->gpu_address; in cik_sdma_copy_buffer() 50 src_offset += rsrc->gpu_address; in cik_sdma_copy_buffer() 93 offset += rdst->gpu_address; in cik_sdma_clear_buffer() 152 uint64_t dst_address = rdst->resource.gpu_address + in cik_sdma_copy_texture() 154 uint64_t src_address = rsrc->resource.gpu_address + in cik_sdma_copy_texture()
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D | si_pm4.c | 154 radeon_emit(cs, ib->gpu_address); in si_pm4_emit() 155 radeon_emit(cs, (ib->gpu_address >> 32) & 0xffff); in si_pm4_emit()
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D | si_state_draw.c | 546 uint64_t va = t->buf_filled_size->gpu_address + in si_emit_draw_packets() 596 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset; in si_emit_draw_packets() 634 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; in si_emit_draw_packets() 684 count_va = params_buf->gpu_address + info->indirect_params_offset; in si_emit_draw_packets() 1282 radeon_emit(cs, sctx->trace_buf->gpu_address); in si_trace_emit() 1283 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32); in si_trace_emit()
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D | si_state_shaders.c | 354 va = shader->bo->gpu_address; in si_shader_ls() 382 va = shader->bo->gpu_address; in si_shader_hs() 410 va = shader->bo->gpu_address; in si_shader_es() 511 va = shader->bo->gpu_address; in si_shader_gs() 565 va = shader->bo->gpu_address; in si_shader_vs() 807 va = shader->bo->gpu_address; in si_shader_ps() 2075 uint64_t scratch_va = sctx->scratch_buffer->gpu_address; in si_update_scratch_buffer() 2275 r600_resource(sctx->tf_ring)->gpu_address >> 8); in si_init_tess_factor_ring() 2284 r600_resource(sctx->tf_ring)->gpu_address >> 8); in si_init_tess_factor_ring()
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D | si_uvd.c | 107 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address( in si_video_buffer_create()
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D | si_state.c | 2216 s_offs = z_offs = rtex->resource.gpu_address; in si_init_depth_surface() 2285 uint64_t va = rtex->htile_buffer->gpu_address; in si_init_depth_surface() 2551 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8; in si_emit_framebuffer_state() 2561 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8; in si_emit_framebuffer_state() 2601 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + in si_emit_framebuffer_state() 2977 va = tex->resource.gpu_address + tex->fmask.offset; in si_make_texture_descriptor() 3925 uint64_t border_color_va = sctx->border_color_buffer->gpu_address; in si_init_config()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | r600_buffer_common.c | 212 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf); in r600_alloc_resource() 214 res->gpu_address = 0; in r600_alloc_resource() 224 res->gpu_address, res->gpu_address + res->buf->size, in r600_alloc_resource() 587 rbuffer->gpu_address = in r600_buffer_from_user_memory() 590 rbuffer->gpu_address = 0; in r600_buffer_from_user_memory()
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D | r600_streamout.c | 210 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address; in r600_emit_streamout_begin() 236 uint64_t va = t[i]->buf_filled_size->gpu_address + in r600_emit_streamout_begin() 282 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in r600_emit_streamout_end()
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D | r600_texture.c | 332 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask() 462 rtex->resource.gpu_address = new_tex->resource.gpu_address; in r600_degrade_tile_mode_to_linear() 781 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; in r600_texture_alloc_cmask_separate() 1094 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf); in r600_texture_create_object() 1121 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_create_object() 1125 rtex->resource.gpu_address, in r600_texture_create_object() 1126 rtex->resource.gpu_address + rtex->resource.buf->size, in r600_texture_create_object() 1418 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_invalidate_storage() 2121 tex->dcc_offset = tex->dcc_separate_buffer->gpu_address; in vi_separate_dcc_try_enable()
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D | r600_query.c | 645 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_start() 726 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_stop() 781 uint64_t va = qbuf->buf->gpu_address; in r600_emit_query_predication() 1500 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in r600_query_hw_get_result_resource() 1639 radeon_emit(cs, buffer->gpu_address); in r600_query_init_backend_mask() 1640 radeon_emit(cs, buffer->gpu_address >> 32); in r600_query_init_backend_mask()
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D | r600_pipe_common.h | 177 uint64_t gpu_address; member
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/external/mesa3d/src/amd/vulkan/ |
D | radv_image.c | 166 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo); in radv_make_buffer_descriptor() local 167 uint64_t va = gpu_address + buffer->offset; in radv_make_buffer_descriptor() 198 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset; in si_set_mutable_tex_desc_fields() local 199 uint64_t va = gpu_address + base_level_info->offset; in si_set_mutable_tex_desc_fields() 217 state[7] = (gpu_address + in si_set_mutable_tex_desc_fields() 340 uint64_t gpu_address = device->ws->buffer_get_va(image->bo); in si_make_texture_descriptor() local 343 va = gpu_address + image->offset + image->fmask.offset; in si_make_texture_descriptor()
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