| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
281 bits<4> imm4;
289 let Inst{3-0} = imm4;
429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1256 void clrex(int imm4 = 0xf);
2817 static Instr CRm(int imm4) { in CRm() argument
2818 VIXL_ASSERT(IsUint4(imm4)); in CRm()
2819 return imm4 << CRm_offset; in CRm()
2822 static Instr CRn(int imm4) { in CRn() argument
2823 VIXL_ASSERT(IsUint4(imm4)); in CRn()
2824 return imm4 << CRn_offset; in CRn()
3011 static Instr ImmNEONExt(int imm4) { in ImmNEONExt() argument
3012 VIXL_ASSERT(IsUint4(imm4)); in ImmNEONExt()
3013 return imm4 << ImmNEONExt_offset; in ImmNEONExt()
[all …]
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| D | disasm-aarch64.cc | 4492 unsigned imm4 = instr->GetImmNEON4(); in SubstituteImmediateField() local
4496 rn_index = imm4 >> tz; in SubstituteImmediateField()
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| D | simulator-aarch64.cc | 3881 int imm4 = instr->GetImmNEON4(); in VisitNEONCopy() local
3882 int rn_index = imm4 >> tz; in VisitNEONCopy()
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| D | assembler-aarch64.cc | 2061 void Assembler::clrex(int imm4) { Emit(CLREX | CRm(imm4)); } in clrex() argument
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| /external/valgrind/VEX/priv/ |
| D | host_arm_isel.c | 3470 UInt imm4; in iselNeon64Expr_wrk() local
3474 imm4 = (index << 1) + 1; in iselNeon64Expr_wrk()
3482 imm4, False in iselNeon64Expr_wrk()
3489 UInt imm4; in iselNeon64Expr_wrk() local
3493 imm4 = (index << 2) + 2; in iselNeon64Expr_wrk()
3501 imm4, False in iselNeon64Expr_wrk()
3508 UInt imm4; in iselNeon64Expr_wrk() local
3512 imm4 = (index << 3) + 4; in iselNeon64Expr_wrk()
3520 imm4, False in iselNeon64Expr_wrk()
3883 UInt imm4; in iselNeon64Expr_wrk() local
[all …]
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| D | host_arm_defs.h | 247 UShort imm4; member
256 extern ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 );
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| D | guest_arm64_toIR.c | 8541 UInt imm4 = INSN(14,11); in dis_AdvSIMD_EXT() local
8553 if (imm4 == 0) { in dis_AdvSIMD_EXT()
8556 vassert(imm4 >= 1 && imm4 <= 15); in dis_AdvSIMD_EXT()
8558 mkexpr(sHi), mkexpr(sLo), mkU8(imm4))); in dis_AdvSIMD_EXT()
8561 DIP("ext v%u.16b, v%u.16b, v%u.16b, #%u\n", dd, nn, mm, imm4); in dis_AdvSIMD_EXT()
8563 if (imm4 >= 8) return False; in dis_AdvSIMD_EXT()
8564 if (imm4 == 0) { in dis_AdvSIMD_EXT()
8567 vassert(imm4 >= 1 && imm4 <= 7); in dis_AdvSIMD_EXT()
8572 mkexpr(hi64lo64), mkexpr(hi64lo64), mkU8(imm4))); in dis_AdvSIMD_EXT()
8575 DIP("ext v%u.8b, v%u.8b, v%u.8b, #%u\n", dd, nn, mm, imm4); in dis_AdvSIMD_EXT()
[all …]
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| D | host_arm_defs.c | 423 ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 ) { in ARMRI84_I84() argument
427 ri84->ARMri84.I84.imm4 = imm4; in ARMRI84_I84()
429 vassert(imm4 >= 0 && imm4 <= 15); in ARMRI84_I84()
443 2 * ri84->ARMri84.I84.imm4)); in ppARMRI84()
2881 vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F)); in skeletal_RI84()
2884 instr |= (ri->ARMri84.I84.imm4 << 8); in skeletal_RI84()
4745 UInt imm4 = imm & 0xF; in emit_ARMInstr() local
4780 cmode, BITS4(0,Q,op,1), imm4); in emit_ARMInstr()
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| D | guest_arm_toIR.c | 2889 UInt imm4 = (theInstr >> 8) & 0xf; in dis_neon_vext() local
2895 /*loV128*/getQReg(nreg), mkU8(imm4)), condT); in dis_neon_vext()
2898 /*loI64*/getDRegI64(nreg), mkU8(imm4)), condT); in dis_neon_vext()
2901 reg_t, mreg, imm4); in dis_neon_vext()
3017 UInt imm4 = (theInstr >> 16) & 0xF; in dis_neon_vdup() local
3024 if ((imm4 == 0) || (imm4 == 8)) in dis_neon_vdup()
3036 if ((imm4 & 1) == 1) { in dis_neon_vdup()
3039 index = imm4 >> 1; in dis_neon_vdup()
3041 } else if ((imm4 & 3) == 2) { in dis_neon_vdup()
3044 index = imm4 >> 2; in dis_neon_vdup()
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| D | host_arm64_defs.c | 5283 UInt imm4 = i->ARM64in.VExtV.amtB; in emit_ARM64Instr() local
5284 vassert(imm4 >= 1 && imm4 <= 15); in emit_ARM64Instr()
5286 X000000 | (imm4 << 1), vN, vD); in emit_ARM64Instr()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 371 # invalid imm4 value (0b1xxx)
372 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | README.txt | 78 | Ks4 | imm4 | |
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| /external/v8/src/arm/ |
| D | disasm-arm.cc | 2015 int imm4 = instr->Bits(11, 8); in DecodeSpecialCondition() local
2021 Vd, Vn, Vm, imm4); in DecodeSpecialCondition()
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| D | assembler-arm.cc | 3158 int imm4 = (imm5 >> 1) & 0xf; in vcvt_f64_s32() local
3160 vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4); in vcvt_f64_s32()
4011 int imm4 = 4 | index << 3; // esize = 32, index in bit 3. in vdup() local
4017 emit(0x1E7U * B23 | d * B22 | 0x3 * B20 | imm4 * B16 | vd * B12 | 0x18 * B7 | in vdup()
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| D | simulator-arm.cc | 4446 int imm4 = instr->Bits(11, 8); in DecodeSpecialCondition() local
4453 int boundary = kSimd128Size - imm4; in DecodeSpecialCondition()
4456 dst[i] = src1[i + imm4]; in DecodeSpecialCondition()
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.cc | 17469 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17471 rm.Encode(5, 0) | (imm4 << 8)); in vext()
17489 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17491 rm.Encode(5, 0) | (imm4 << 8)); in vext()
17526 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17528 rm.Encode(5, 0) | (imm4 << 8)); in vext()
17546 uint32_t imm4 = imm / dt.GetSize(); in vext() local
17548 rm.Encode(5, 0) | (imm4 << 8)); in vext()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 269 void clrex(int imm4 = 0xf)
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 6161 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
6166 let Inst{14-11} = imm4;
|