Searched refs:isInsertSubreg (Results 1 – 21 of 21) sorted by relevance
105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()171 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
254 if (MI->isInsertSubreg()) { in optimizeSDPattern()337 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
3690 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() || in getOperandLatency()3986 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()4006 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
5913 let isInsertSubreg = 1;
102 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()125 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
2342 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || in getOperandLatency()2672 if (MI->isCopyLike() || MI->isInsertSubreg() || in getInstrLatency()
67 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
198 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()968 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()1765 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()1904 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
1174 assert((MI.isInsertSubreg() || in getInsertSubregInputs()1177 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
387 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { in isCopyToReg()1692 if (mi->isInsertSubreg()) { in runOnMachineFunction()
1812 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { in print()
257 bool isInsertSubreg : 1; variable
508 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; in emitRecord()
325 isInsertSubreg = R->getValueAsBit("isInsertSubreg"); in CodeGenInstruction()
275 bool isInsertSubreg() const {
382 return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence(); in AvoidsSinking()
400 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { in isCopyToReg()1254 if (mi->isInsertSubreg()) { in runOnMachineFunction()
1459 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { in print()
805 bool isInsertSubreg() const {
271 return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence(); in shouldSink()
397 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?