| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ldxr-stxr.ll | 179 %val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
193 %val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
202 ; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
207 %val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
216 ; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
219 %val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
225 declare i64 @llvm.aarch64.ldaxr.p0i8(i8*) nounwind
226 declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
227 declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
228 declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
|
| D | cmpxchg-idioms.ll | 7 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
62 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
|
| D | cmpxchg-O0.ll | 36 ; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]
51 ; CHECK: ldaxr [[OLD:x[0-9]+]], [x0]
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| D | arm64-atomic.ll | 7 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
25 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
44 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]
94 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
108 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
|
| D | atomic-ops.ll | 143 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
163 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
223 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
243 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
303 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
383 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
480 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
573 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
743 ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
767 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 510 ldaxr w2, [x4]
511 ldaxr x2, [x4]
517 ; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
518 ; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
|
| D | basic-a64-instructions.s | 2296 ldaxr wzr, [x22]
2297 ldaxr x21, [x23]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-memory.txt | 498 # CHECK: ldaxr w2, [x4]
499 # CHECK: ldaxr x2, [x4]
|
| D | basic-a64-instructions.txt | 1966 #CHECK: ldaxr w6, [sp]
1967 #CHECK: ldaxr x5, [x6]
1968 #CHECK: ldaxr x5, [x6]
1969 #CHECK: ldaxr x5, [x6]
|
| /external/vixl/ |
| D | README.md | 125 `stlxrh`, `stlxr`, `ldaxrb`, `ldaxrh`, `ldaxr`, `stlxp`, `ldaxp`, `stlrb`,
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 894 0xdf,0xfe,0x5f,0x88 = ldaxr wzr, [x22]
895 0xf5,0xfe,0x5f,0xc8 = ldaxr x21, [x23]
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 77 V(Ldaxr, ldaxr) \
|
| D | assembler-arm64.h | 1405 void ldaxr(const Register& rt, const Register& rn);
|
| D | assembler-arm64.cc | 1703 void Assembler::ldaxr(const Register& rt, const Register& rn) { in ldaxr() function in v8::internal::Assembler
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1827 COMPARE(ldaxr(w21, MemOperand(x22)), "ldaxr w21, [x22]"); in TEST()
1828 COMPARE(ldaxr(w23, MemOperand(sp)), "ldaxr w23, [sp]"); in TEST()
1829 COMPARE(ldaxr(x24, MemOperand(x25)), "ldaxr x24, [x25]"); in TEST()
1830 COMPARE(ldaxr(x26, MemOperand(sp)), "ldaxr x26, [sp]"); in TEST()
|
| D | test-trace-aarch64.cc | 160 __ ldaxr(w13, MemOperand(x0)); in GenerateTestSequenceBase() local
161 __ ldaxr(x14, MemOperand(x0)); in GenerateTestSequenceBase() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1147 void ldaxr(const Register& rt, const MemOperand& src);
|
| D | macro-assembler-aarch64.h | 1481 ldaxr(rt, src); in Ldaxr()
|
| D | assembler-aarch64.cc | 1325 void Assembler::ldaxr(const Register& rt, const MemOperand& src) { in ldaxr() function in vixl::aarch64::Assembler
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 106 0x~~~~~~~~~~~~~~~~ 885ffc0d ldaxr w13, [x0]
107 0x~~~~~~~~~~~~~~~~ c85ffc0e ldaxr x14, [x0]
|
| D | log-disasm | 106 0x~~~~~~~~~~~~~~~~ 885ffc0d ldaxr w13, [x0]
107 0x~~~~~~~~~~~~~~~~ c85ffc0e ldaxr x14, [x0]
|
| D | log-all | 278 0x~~~~~~~~~~~~~~~~ 885ffc0d ldaxr w13, [x0]
280 0x~~~~~~~~~~~~~~~~ c85ffc0e ldaxr x14, [x0]
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 529 void ldaxr(const Register& rt, const MemOperand& src)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2438 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2439 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 190 aarch64_ldaxr, // llvm.aarch64.ldaxr
6248 "llvm.aarch64.ldaxr",
14188 3, // llvm.aarch64.ldaxr
|