| /external/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_deadlock_detector2.cc | 91 void DestroyLogicalThread(DDLogicalThread *lt);
102 void CycleCheck(DDPhysicalThread *pt, DDLogicalThread *lt, DDMutex *mtx);
103 void Report(DDPhysicalThread *pt, DDLogicalThread *lt, int npath);
141 DDLogicalThread *lt = (DDLogicalThread*)InternalAlloc( in CreateLogicalThread() local
143 lt->ctx = ctx; in CreateLogicalThread()
144 lt->nlocked = 0; in CreateLogicalThread()
145 return lt; in CreateLogicalThread()
148 void DD::DestroyLogicalThread(DDLogicalThread *lt) { in DestroyLogicalThread() argument
149 lt->~DDLogicalThread(); in DestroyLogicalThread()
150 InternalFree(lt); in DestroyLogicalThread()
[all …]
|
| D | sanitizer_deadlock_detector1.cc | 47 void DestroyLogicalThread(DDLogicalThread *lt) override;
58 void MutexEnsureID(DDLogicalThread *lt, DDMutex *m);
81 DDLogicalThread *lt = (DDLogicalThread*)InternalAlloc(sizeof(*lt)); in CreateLogicalThread() local
82 lt->ctx = ctx; in CreateLogicalThread()
83 lt->dd.clear(); in CreateLogicalThread()
84 lt->report_pending = false; in CreateLogicalThread()
85 return lt; in CreateLogicalThread()
88 void DD::DestroyLogicalThread(DDLogicalThread *lt) { in DestroyLogicalThread() argument
89 lt->~DDLogicalThread(); in DestroyLogicalThread()
90 InternalFree(lt); in DestroyLogicalThread()
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc | 104 {{lt, r0, r0, 203}, true, lt, "lt r0 r0 203", "lt_r0_r0_203"},
113 {{lt, r3, r3, 207}, true, lt, "lt r3 r3 207", "lt_r3_r3_207"},
125 {{lt, r1, r1, 158}, true, lt, "lt r1 r1 158", "lt_r1_r1_158"},
130 {{lt, r7, r7, 224}, true, lt, "lt r7 r7 224", "lt_r7_r7_224"},
147 {{lt, r3, r3, 43}, true, lt, "lt r3 r3 43", "lt_r3_r3_43"},
172 {{lt, r6, r6, 229}, true, lt, "lt r6 r6 229", "lt_r6_r6_229"},
173 {{lt, r4, r4, 128}, true, lt, "lt r4 r4 128", "lt_r4_r4_128"},
193 {{lt, r4, r4, 57}, true, lt, "lt r4 r4 57", "lt_r4_r4_57"},
197 {{lt, r4, r4, 216}, true, lt, "lt r4 r4 216", "lt_r4_r4_216"},
202 {{lt, r5, r5, 215}, true, lt, "lt r5 r5 215", "lt_r5_r5_215"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-in-it-block-t32.cc | 2571 {{lt, r0, r0}, true, lt, "lt r0 r0", "lt_r0_r0"},
2572 {{lt, r0, r1}, true, lt, "lt r0 r1", "lt_r0_r1"},
2573 {{lt, r0, r2}, true, lt, "lt r0 r2", "lt_r0_r2"},
2574 {{lt, r0, r3}, true, lt, "lt r0 r3", "lt_r0_r3"},
2575 {{lt, r0, r4}, true, lt, "lt r0 r4", "lt_r0_r4"},
2576 {{lt, r0, r5}, true, lt, "lt r0 r5", "lt_r0_r5"},
2577 {{lt, r0, r6}, true, lt, "lt r0 r6", "lt_r0_r6"},
2578 {{lt, r0, r7}, true, lt, "lt r0 r7", "lt_r0_r7"},
2579 {{lt, r0, r8}, true, lt, "lt r0 r8", "lt_r0_r8"},
2580 {{lt, r0, r9}, true, lt, "lt r0 r9", "lt_r0_r9"},
[all …]
|
| D | test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc | 104 {{lt, r4, 152}, true, lt, "lt r4 152", "lt_r4_152"},
113 {{lt, r4, 185}, true, lt, "lt r4 185", "lt_r4_185"},
117 {{lt, r7, 97}, true, lt, "lt r7 97", "lt_r7_97"},
124 {{lt, r4, 103}, true, lt, "lt r4 103", "lt_r4_103"},
130 {{lt, r4, 49}, true, lt, "lt r4 49", "lt_r4_49"},
160 {{lt, r4, 39}, true, lt, "lt r4 39", "lt_r4_39"},
164 {{lt, r3, 206}, true, lt, "lt r3 206", "lt_r3_206"},
214 {{lt, r5, 192}, true, lt, "lt r5 192", "lt_r5_192"},
310 {{lt, r1, 139}, true, lt, "lt r1 139", "lt_r1_139"},
322 {{lt, r4, 67}, true, lt, "lt r4 67", "lt_r4_67"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc | 799 {{lt, r0, r0}, true, lt, "lt r0 r0", "lt_r0_r0"},
800 {{lt, r0, r1}, true, lt, "lt r0 r1", "lt_r0_r1"},
801 {{lt, r0, r2}, true, lt, "lt r0 r2", "lt_r0_r2"},
802 {{lt, r0, r3}, true, lt, "lt r0 r3", "lt_r0_r3"},
803 {{lt, r0, r4}, true, lt, "lt r0 r4", "lt_r0_r4"},
804 {{lt, r0, r5}, true, lt, "lt r0 r5", "lt_r0_r5"},
805 {{lt, r0, r6}, true, lt, "lt r0 r6", "lt_r0_r6"},
806 {{lt, r0, r7}, true, lt, "lt r0 r7", "lt_r0_r7"},
807 {{lt, r1, r0}, true, lt, "lt r1 r0", "lt_r1_r0"},
808 {{lt, r1, r1}, true, lt, "lt r1 r1", "lt_r1_r1"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc | 799 {{lt, r0, r0, 0}, true, lt, "lt r0 r0 0", "lt_r0_r0_0"},
800 {{lt, r0, r1, 0}, true, lt, "lt r0 r1 0", "lt_r0_r1_0"},
801 {{lt, r0, r2, 0}, true, lt, "lt r0 r2 0", "lt_r0_r2_0"},
802 {{lt, r0, r3, 0}, true, lt, "lt r0 r3 0", "lt_r0_r3_0"},
803 {{lt, r0, r4, 0}, true, lt, "lt r0 r4 0", "lt_r0_r4_0"},
804 {{lt, r0, r5, 0}, true, lt, "lt r0 r5 0", "lt_r0_r5_0"},
805 {{lt, r0, r6, 0}, true, lt, "lt r0 r6 0", "lt_r0_r6_0"},
806 {{lt, r0, r7, 0}, true, lt, "lt r0 r7 0", "lt_r0_r7_0"},
807 {{lt, r1, r0, 0}, true, lt, "lt r1 r0 0", "lt_r1_r0_0"},
808 {{lt, r1, r1, 0}, true, lt, "lt r1 r1 0", "lt_r1_r1_0"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc | 105 {{lt, r4, r5, 7}, true, lt, "lt r4 r5 7", "lt_r4_r5_7"},
106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
121 {{lt, r5, r2, 0}, true, lt, "lt r5 r2 0", "lt_r5_r2_0"},
136 {{lt, r7, r5, 2}, true, lt, "lt r7 r5 2", "lt_r7_r5_2"},
146 {{lt, r0, r4, 5}, true, lt, "lt r0 r4 5", "lt_r0_r4_5"},
151 {{lt, r1, r5, 5}, true, lt, "lt r1 r5 5", "lt_r1_r5_5"},
179 {{lt, r1, r5, 4}, true, lt, "lt r1 r5 4", "lt_r1_r5_4"},
183 {{lt, r5, r1, 0}, true, lt, "lt r5 r1 0", "lt_r5_r1_0"},
190 {{lt, r2, r0, 5}, true, lt, "lt r2 r0 5", "lt_r2_r0_5"},
214 {{lt, r4, r0, 6}, true, lt, "lt r4 r0 6", "lt_r4_r0_6"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc | 111 {{lt, r0, r0, r4}, true, lt, "lt r0 r0 r4", "lt_r0_r0_r4"},
133 {{lt, r0, r0, r2}, true, lt, "lt r0 r0 r2", "lt_r0_r0_r2"},
163 {{lt, r2, r2, r1}, true, lt, "lt r2 r2 r1", "lt_r2_r2_r1"},
170 {{lt, r2, r2, r7}, true, lt, "lt r2 r2 r7", "lt_r2_r2_r7"},
187 {{lt, r4, r4, r0}, true, lt, "lt r4 r4 r0", "lt_r4_r4_r0"},
200 {{lt, r5, r5, r5}, true, lt, "lt r5 r5 r5", "lt_r5_r5_r5"},
220 {{lt, r3, r3, r7}, true, lt, "lt r3 r3 r7", "lt_r3_r3_r7"},
230 {{lt, r5, r5, r2}, true, lt, "lt r5 r5 r2", "lt_r5_r5_r2"},
231 {{lt, r6, r6, r4}, true, lt, "lt r6 r6 r4", "lt_r6_r6_r4"},
234 {{lt, r4, r4, r5}, true, lt, "lt r4 r4 r5", "lt_r4_r4_r5"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc | 799 {{lt, r0, r0, r0}, true, lt, "lt r0 r0 r0", "lt_r0_r0_r0"},
800 {{lt, r0, r1, r0}, true, lt, "lt r0 r1 r0", "lt_r0_r1_r0"},
801 {{lt, r0, r2, r0}, true, lt, "lt r0 r2 r0", "lt_r0_r2_r0"},
802 {{lt, r0, r3, r0}, true, lt, "lt r0 r3 r0", "lt_r0_r3_r0"},
803 {{lt, r0, r4, r0}, true, lt, "lt r0 r4 r0", "lt_r0_r4_r0"},
804 {{lt, r0, r5, r0}, true, lt, "lt r0 r5 r0", "lt_r0_r5_r0"},
805 {{lt, r0, r6, r0}, true, lt, "lt r0 r6 r0", "lt_r0_r6_r0"},
806 {{lt, r0, r7, r0}, true, lt, "lt r0 r7 r0", "lt_r0_r7_r0"},
807 {{lt, r1, r0, r1}, true, lt, "lt r1 r0 r1", "lt_r1_r0_r1"},
808 {{lt, r1, r1, r1}, true, lt, "lt r1 r1 r1", "lt_r1_r1_r1"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc | 98 {{lt, r5, r3, LSL, 21}, true, lt, "lt r5 r3 LSL 21", "lt_r5_r3_LSL_21"},
102 {{lt, r4, r2, LSL, 31}, true, lt, "lt r4 r2 LSL 31", "lt_r4_r2_LSL_31"},
117 {{lt, r0, r0, LSL, 27}, true, lt, "lt r0 r0 LSL 27", "lt_r0_r0_LSL_27"},
125 {{lt, r4, r5, LSL, 25}, true, lt, "lt r4 r5 LSL 25", "lt_r4_r5_LSL_25"},
141 {{lt, r7, r3, LSL, 28}, true, lt, "lt r7 r3 LSL 28", "lt_r7_r3_LSL_28"},
156 {{lt, r4, r6, LSL, 19}, true, lt, "lt r4 r6 LSL 19", "lt_r4_r6_LSL_19"},
163 {{lt, r5, r3, LSL, 20}, true, lt, "lt r5 r3 LSL 20", "lt_r5_r3_LSL_20"},
178 {{lt, r0, r0, LSL, 14}, true, lt, "lt r0 r0 LSL 14", "lt_r0_r0_LSL_14"},
191 {{lt, r2, r3, LSL, 3}, true, lt, "lt r2 r3 LSL 3", "lt_r2_r3_LSL_3"},
195 {{lt, r5, r0, LSL, 14}, true, lt, "lt r5 r0 LSL 14", "lt_r5_r0_LSL_14"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 152 {{lt, r2, r1, LSR, 2}, true, lt, "lt r2 r1 LSR 2", "lt_r2_r1_LSR_2"},
163 {{lt, r5, r4, LSR, 26}, true, lt, "lt r5 r4 LSR 26", "lt_r5_r4_LSR_26"},
171 {{lt, r5, r0, ASR, 4}, true, lt, "lt r5 r0 ASR 4", "lt_r5_r0_ASR_4"},
178 {{lt, r5, r2, LSR, 1}, true, lt, "lt r5 r2 LSR 1", "lt_r5_r2_LSR_1"},
179 {{lt, r7, r0, LSR, 13}, true, lt, "lt r7 r0 LSR 13", "lt_r7_r0_LSR_13"},
192 {{lt, r1, r1, LSR, 1}, true, lt, "lt r1 r1 LSR 1", "lt_r1_r1_LSR_1"},
200 {{lt, r4, r0, LSR, 5}, true, lt, "lt r4 r0 LSR 5", "lt_r4_r0_LSR_5"},
207 {{lt, r7, r6, ASR, 15}, true, lt, "lt r7 r6 ASR 15", "lt_r7_r6_ASR_15"},
211 {{lt, r5, r4, LSR, 5}, true, lt, "lt r5 r4 LSR 5", "lt_r5_r4_LSR_5"},
220 {{lt, r6, r5, ASR, 15}, true, lt, "lt r6 r5 ASR 15", "lt_r6_r5_ASR_15"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc | 111 {{lt, r3, r3, r4}, true, lt, "lt r3 r3 r4", "lt_r3_r3_r4"},
123 {{lt, r13, r13, r14}, true, lt, "lt r13 r13 r14", "lt_r13_r13_r14"},
131 {{lt, r2, r2, r11}, true, lt, "lt r2 r2 r11", "lt_r2_r2_r11"},
162 {{lt, r14, r14, r9}, true, lt, "lt r14 r14 r9", "lt_r14_r14_r9"},
173 {{lt, r13, r13, r9}, true, lt, "lt r13 r13 r9", "lt_r13_r13_r9"},
188 {{lt, r9, r9, r7}, true, lt, "lt r9 r9 r7", "lt_r9_r9_r7"},
205 {{lt, r1, r1, r5}, true, lt, "lt r1 r1 r5", "lt_r1_r1_r5"},
228 {{lt, r11, r11, r11}, true, lt, "lt r11 r11 r11", "lt_r11_r11_r11"},
246 {{lt, r4, r4, r8}, true, lt, "lt r4 r4 r8", "lt_r4_r4_r8"},
251 {{lt, r3, r3, r10}, true, lt, "lt r3 r3 r10", "lt_r3_r3_r10"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 137 {{lt, r4, r4, ROR, r3}, true, lt, "lt r4 r4 ROR r3", "lt_r4_r4_ROR_r3"},
149 {{lt, r0, r0, LSR, r0}, true, lt, "lt r0 r0 LSR r0", "lt_r0_r0_LSR_r0"},
160 {{lt, r5, r5, LSR, r4}, true, lt, "lt r5 r5 LSR r4", "lt_r5_r5_LSR_r4"},
181 {{lt, r6, r6, LSR, r5}, true, lt, "lt r6 r6 LSR r5", "lt_r6_r6_LSR_r5"},
194 {{lt, r1, r1, LSR, r2}, true, lt, "lt r1 r1 LSR r2", "lt_r1_r1_LSR_r2"},
195 {{lt, r4, r4, LSL, r4}, true, lt, "lt r4 r4 LSL r4", "lt_r4_r4_LSL_r4"},
212 {{lt, r5, r5, LSL, r5}, true, lt, "lt r5 r5 LSL r5", "lt_r5_r5_LSL_r5"},
228 {{lt, r3, r3, ASR, r2}, true, lt, "lt r3 r3 ASR r2", "lt_r3_r3_ASR_r2"},
251 {{lt, r0, r0, ASR, r4}, true, lt, "lt r0 r0 ASR r4", "lt_r0_r0_ASR_r4"},
255 {{lt, r6, r6, ROR, r3}, true, lt, "lt r6 r6 ROR r3", "lt_r6_r6_ROR_r3"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-a32.cc | 96 {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
117 {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
135 {{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
136 {{lt, r14, r3}, "lt, r14, r3", "lt_r14_r3"},
145 {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
171 {{lt, r7, r13}, "lt, r7, r13", "lt_r7_r13"},
201 {{lt, r4, r10}, "lt, r4, r10", "lt_r4_r10"},
213 {{lt, r12, r3}, "lt, r12, r3", "lt_r12_r3"},
229 {{lt, r4, r12}, "lt, r4, r12", "lt_r4_r12"},
245 {{lt, r5, r11}, "lt, r5, r11", "lt_r5_r11"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-t32.cc | 96 {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
117 {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
135 {{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
136 {{lt, r14, r3}, "lt, r14, r3", "lt_r14_r3"},
145 {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
171 {{lt, r7, r13}, "lt, r7, r13", "lt_r7_r13"},
201 {{lt, r4, r10}, "lt, r4, r10", "lt_r4_r10"},
213 {{lt, r12, r3}, "lt, r12, r3", "lt_r12_r3"},
229 {{lt, r4, r12}, "lt, r4, r12", "lt_r4_r12"},
245 {{lt, r5, r11}, "lt, r5, r11", "lt_r5_r11"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc | 113 {{lt, r4, r3, r3}, true, lt, "lt r4 r3 r3", "lt_r4_r3_r3"},
121 {{lt, r3, r5, r2}, true, lt, "lt r3 r5 r2", "lt_r3_r5_r2"},
125 {{lt, r6, r3, r3}, true, lt, "lt r6 r3 r3", "lt_r6_r3_r3"},
138 {{lt, r6, r4, r1}, true, lt, "lt r6 r4 r1", "lt_r6_r4_r1"},
184 {{lt, r0, r5, r3}, true, lt, "lt r0 r5 r3", "lt_r0_r5_r3"},
193 {{lt, r4, r5, r7}, true, lt, "lt r4 r5 r7", "lt_r4_r5_r7"},
216 {{lt, r0, r0, r5}, true, lt, "lt r0 r0 r5", "lt_r0_r0_r5"},
291 {{lt, r0, r5, r1}, true, lt, "lt r0 r5 r1", "lt_r0_r5_r1"},
298 {{lt, r7, r4, r2}, true, lt, "lt r7 r4 r2", "lt_r7_r4_r2"},
316 {{lt, r4, r1, r5}, true, lt, "lt r4 r1 r5", "lt_r4_r1_r5"},
[all …]
|
| /external/eigen/bench/btl/data/ |
| D | perlib_plot_settings.txt | 1 eigen3 ; with lines lw 4 lt 1 lc rgbcolor "black"
2 eigen2 ; with lines lw 3 lt 1 lc rgbcolor "#999999"
3 EigenBLAS ; with lines lw 3 lt 3 lc rgbcolor "#999999"
4 eigen3_novec ; with lines lw 2 lt 1 lc rgbcolor "#999999"
5 eigen3_nogccvec ; with lines lw 2 lt 2 lc rgbcolor "#991010"
6 INTEL_MKL ; with lines lw 3 lt 1 lc rgbcolor "#ff0000"
7 ATLAS ; with lines lw 3 lt 1 lc rgbcolor "#008000"
8 gmm ; with lines lw 3 lt 1 lc rgbcolor "#0000ff"
9 ublas ; with lines lw 3 lt 1 lc rgbcolor "#00b7ff"
10 mtl4 ; with lines lw 3 lt 1 lc rgbcolor "#d18847"
[all …]
|
| /external/python/cpython3/Modules/_ctypes/libffi/src/ia64/ |
| D | unix.S | 179 cmp.lt p6, p0 = 8, in3
180 cmp.lt p7, p0 = 16, in3
181 cmp.lt p8, p0 = 24, in3
203 cmp.lt p6, p0 = 4, in3
207 cmp.lt p7, p0 = 8, in3
208 cmp.lt p8, p0 = 12, in3
212 cmp.lt p9, p0 = 16, in3
213 cmp.lt p10, p0 = 20, in3
217 cmp.lt p6, p0 = 24, in3
218 cmp.lt p7, p0 = 28, in3
[all …]
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/ia64/ |
| D | unix.S | 179 cmp.lt p6, p0 = 8, in3
180 cmp.lt p7, p0 = 16, in3
181 cmp.lt p8, p0 = 24, in3
203 cmp.lt p6, p0 = 4, in3
207 cmp.lt p7, p0 = 8, in3
208 cmp.lt p8, p0 = 12, in3
212 cmp.lt p9, p0 = 16, in3
213 cmp.lt p10, p0 = 20, in3
217 cmp.lt p6, p0 = 24, in3
218 cmp.lt p7, p0 = 28, in3
[all …]
|
| /external/libffi/src/ia64/ |
| D | unix.S | 179 cmp.lt p6, p0 = 8, in3
180 cmp.lt p7, p0 = 16, in3
181 cmp.lt p8, p0 = 24, in3
203 cmp.lt p6, p0 = 4, in3
207 cmp.lt p7, p0 = 8, in3
208 cmp.lt p8, p0 = 12, in3
212 cmp.lt p9, p0 = 16, in3
213 cmp.lt p10, p0 = 20, in3
217 cmp.lt p6, p0 = 24, in3
218 cmp.lt p7, p0 = 28, in3
[all …]
|
| /external/tensorflow/tensorflow/contrib/labeled_tensor/python/ops/ |
| D | core_test.py | 170 self.lt = core.LabeledTensor(tensor, [a0, a1, a2, a3])
180 self.assertRegexpMatches(repr(self.lt), regexp)
183 alt_lt = core.LabeledTensor(self.lt.tensor, self.lt.axes)
184 self.assertLabeledTensorsEqual(alt_lt, self.lt)
187 alt_lt = core.LabeledTensor(self.lt.tensor, self.lt.axes.values())
188 self.assertLabeledTensorsEqual(alt_lt, self.lt)
191 actual = self.lt[:, :, :, 0]
192 expected = core.LabeledTensor(self.lt.tensor[:, :, :, 0],
193 list(self.lt.axes.values())[:-1])
196 actual = self.lt[1, :, :, 0]
[all …]
|
| /external/scapy/scapy/ |
| D | data.py | 132 lt = tuple(re.split(spaces, l))
133 if len(lt) < 2 or not lt[0]:
135 dct[lt[0]] = int(lt[1])
155 lt = tuple(re.split(spaces, l))
156 if len(lt) < 2 or not lt[0]:
158 dct[lt[0]] = int(lt[1], 16)
180 lt = tuple(re.split(spaces, l))
181 if len(lt) < 2 or not lt[0]:
183 if lt[1].endswith(b"/tcp"):
184 tdct[lt[0]] = int(lt[1].split(b'/')[0])
[all …]
|
| /external/lz4/programs/ |
| D | datagen.c | 71 static void RDG_fillLiteralDistrib(litDistribTable lt, double ld) in RDG_fillLiteralDistrib() argument
81 while (u < end) lt[u++] = character; in RDG_fillLiteralDistrib()
88 static BYTE RDG_genChar(U32* seed, const litDistribTable lt) in RDG_genChar() argument
91 return (lt[id]); in RDG_genChar()
98 …ffer, size_t buffSize, size_t prefixSize, double matchProba, litDistribTable lt, unsigned* seedPtr) in RDG_genBlock() argument
118 buffPtr[pos-1] = RDG_genChar(seed, lt); in RDG_genBlock()
122 if (pos==0) buffPtr[0] = RDG_genChar(seed, lt), pos=1; in RDG_genBlock()
148 while (pos < d) buffPtr[pos++] = RDG_genChar(seed, lt); in RDG_genBlock()
156 litDistribTable lt; in RDG_genBuffer() local
158 RDG_fillLiteralDistrib(lt, litProba); in RDG_genBuffer()
[all …]
|
| /external/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/ |
| D | lt.pass.cpp | 21 assert( std::char_traits<char>::lt('\0', 'A')); in main()
22 assert(!std::char_traits<char>::lt('A', '\0')); in main()
24 assert(!std::char_traits<char>::lt('a', 'a')); in main()
25 assert( std::char_traits<char>::lt('A', 'a')); in main()
26 assert(!std::char_traits<char>::lt('a', 'A')); in main()
28 assert( std::char_traits<char>::lt('a', 'z')); in main()
29 assert( std::char_traits<char>::lt('A', 'Z')); in main()
31 assert( std::char_traits<char>::lt(' ', 'A')); in main()
32 assert( std::char_traits<char>::lt('A', '~')); in main()
|