/external/lzma/Asm/x86/ |
D | XzCrc64Opt.asm | 11 rN equ r10 define 16 SRCDAT equ rN + rD 29 dec rN 36 mov rN, num_VAR 39 test rN, rN 47 cmp rN, 8 49 add rN, rD 50 mov num_VAR, rN 51 sub rN, 4 52 and rN, NOT 3 [all …]
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D | 7zCrcOpt.asm | 9 rN equ r7 define 21 SRCDAT equ rN + rD + 4 * 42 dec rN 49 mov rN, num_VAR 51 test rN, rN 59 cmp rN, 16 61 add rN, rD 62 mov num_VAR, rN 63 sub rN, 8 64 and rN, NOT 7 [all …]
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/external/valgrind/VEX/priv/ |
D | guest_arm_toIR.c | 2396 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, in mk_EA_reg_plusminus_imm12() argument 2399 vassert(rN < 16); in mk_EA_reg_plusminus_imm12() 2403 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12); in mk_EA_reg_plusminus_imm12() 2406 getIRegA(rN), in mk_EA_reg_plusminus_imm12() 2415 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM, in mk_EA_reg_plusminus_shifted_reg() argument 2419 vassert(rN < 16); in mk_EA_reg_plusminus_shifted_reg() 2430 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); in mk_EA_reg_plusminus_shifted_reg() 2440 rN, opChar, rM, imm5 == 0 ? 32 : imm5); in mk_EA_reg_plusminus_shifted_reg() 2452 rN, opChar, rM, imm5 == 0 ? 32 : imm5); in mk_EA_reg_plusminus_shifted_reg() 2463 DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM); in mk_EA_reg_plusminus_shifted_reg() [all …]
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D | host_arm64_defs.c | 1025 ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStH() argument 1030 i->ARM64in.VLdStH.rN = rN; in ARM64Instr_VLdStH() 1035 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStS() argument 1040 i->ARM64in.VLdStS.rN = rN; in ARM64Instr_VLdStS() 1045 ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStD() argument 1050 i->ARM64in.VLdStD.rN = rN; in ARM64Instr_VLdStD() 1055 ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { in ARM64Instr_VLdStQ() argument 1060 i->ARM64in.VLdStQ.rN = rN; in ARM64Instr_VLdStQ() 1594 ppHRegARM64(i->ARM64in.VLdStH.rN); in ppARM64Instr() 1599 ppHRegARM64(i->ARM64in.VLdStH.rN); in ppARM64Instr() [all …]
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D | host_arm64_defs.h | 712 HReg rN; member 719 HReg rN; member 726 HReg rN; member 733 HReg rN; // address member 945 extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, 947 extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, 949 extern ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, 951 extern ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN );
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D | host_arm_defs.c | 365 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { in mkARMAModeN_RR() argument 368 am->ARMamN.RR.rN = rN; in mkARMAModeN_RR() 373 ARMAModeN *mkARMAModeN_R ( HReg rN ) { in mkARMAModeN_R() argument 376 am->ARMamN.R.rN = rN; in mkARMAModeN_R() 382 addHRegUse(u, HRmRead, am->ARMamN.R.rN); in addRegUsage_ARMAModeN() 384 addHRegUse(u, HRmRead, am->ARMamN.RR.rN); in addRegUsage_ARMAModeN() 391 am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN); in mapRegs_ARMAModeN() 393 am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN); in mapRegs_ARMAModeN() 401 ppHRegARM(am->ARMamN.R.rN); in ppARMAModeN() 403 ppHRegARM(am->ARMamN.RR.rN); in ppARMAModeN() [all …]
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D | host_arm_defs.h | 215 HReg rN; member 219 HReg rN; member 970 HReg rN; member 1047 extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 );
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/external/compiler-rt/lib/builtins/arm/ |
D | sync-ops.h | 51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument 52 cmp rN, rM ; \ 55 mov##cmp_kind rD, rN
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D | sync_fetch_and_add_4.S | 18 #define add_4(rD, rN, rM) add rD, rN, rM argument
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D | sync_fetch_and_and_4.S | 17 #define and_4(rD, rN, rM) and rD, rN, rM argument
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D | sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
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D | sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
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D | sync_fetch_and_sub_4.S | 18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
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D | sync_fetch_and_xor_4.S | 17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
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D | sync_fetch_and_max_4.S | 17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
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D | sync_fetch_and_min_4.S | 17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
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D | sync_fetch_and_umax_4.S | 17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
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D | sync_fetch_and_umin_4.S | 17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
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/external/honggfuzz/examples/apache-httpd/corpus_http2/ |
D | d22fda3dd9be202eeac3d4fc1d56438b.00004d7d.honggfuzz.cov | 5 …```````````````````````````````````(�1@�Fl����B �6%|~�*�����ϙ+ۀF�LU�R�!�rN��cĶ5>�>TԽ��tz8i���Z�… 8 …```````````````````````````````````(�1@�Fl����B �6%|~�*�����ϙ+ۀF�LU�R�!�rN��cĶ5>�>TԽ��tz8i���Z�… 11 …```````````````````````````````````(�1@�Fl����B �6%|~�*�����ϙ+ۀF�LU�R�!�rN��cĶ5>�>TԽ��tz8i���Z�…
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D | b1461af2ef9dea09f09e2f5f109e9d03.000016a4.honggfuzz.cov | 33 …�TV��k�����E7����T��'�u�p��)nS"�E4v�~�>+q1;�/&�j�:w¤X�o�����E�'�_�L}��$�rN�N�=3y="����UIhD�N>�…
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D | c65fbaa9f4ee504b0e3c350852c46f99.0000099f.honggfuzz.cov | 17 (Lj�~�7Y�kY�x�d�$�w���q�]\LzJҞ���`�f]�|�c��`�>�S�-bޫ|)]Z�zO��ޠ/�rN��b�]mQ��c���R;q.�Xz��_���…
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/external/llvm/test/CodeGen/ARM/ |
D | varargs-spill-stack-align-nacl.ll | 9 ; stack. A varargs function must therefore spill rN-r3 just below the
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/external/honggfuzz/examples/apache-httpd/corpus_http1/ |
D | 37623cb761ed4f4945734ba8c2db86d8.000004d0.honggfuzz.cov | 10 �yC���MIw��d��Z2�=�r�jU�rN��d����>�Ǧ�)������#��Ky����M-b�(�Ɏ�J�^��-���/� ������'Y���\r0�…
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D | b1461af2ef9dea09f09e2f5f109e9d03.000016a4.honggfuzz.cov | 33 …�TV��k�����E7����T��'�u�p��)nS"�E4v�~�>+q1;�/&�j�:w¤X�o�����E�'�_�L}��$�rN�N�=3y="����UIhD�N>�…
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