| /external/libvpx/libvpx/vpx_ports/ |
| D | asmdefs_mmi.h | 21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
22 "daddu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
24 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
25 "daddiu " #reg1 ", " #reg2 ", " #immediate " \n\t"
27 #define MMI_ADDI(reg1, reg2, immediate) \ argument
28 "daddi " #reg1 ", " #reg2 ", " #immediate " \n\t"
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
31 "dsubu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
36 #define MMI_SRL(reg1, reg2, shift) \ argument
37 "dsrl " #reg1 ", " #reg2 ", " #shift " \n\t"
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1); in idct32x8_row_even_process_store()
75 reg2 = reg1 + reg5; in idct32x8_row_even_process_store()
76 reg1 = reg1 - reg5; in idct32x8_row_even_process_store()
88 DOTP_CONST_PAIR((-reg6), reg1, cospi_24_64, cospi_8_64, reg6, reg1); in idct32x8_row_even_process_store()
92 vec1 = reg7 - reg1; in idct32x8_row_even_process_store()
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| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); in vpx_idct16_1d_rows_msa()
43 reg9 = reg1 - loc2; in vpx_idct16_1d_rows_msa()
44 reg1 = reg1 + loc2; in vpx_idct16_1d_rows_msa()
57 loc1 = reg1 + reg13; in vpx_idct16_1d_rows_msa()
58 reg13 = reg1 - reg13; in vpx_idct16_1d_rows_msa()
71 reg1 = reg6 - loc0; in vpx_idct16_1d_rows_msa()
101 TRANSPOSE8x8_SH_SH(reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15, reg3, in vpx_idct16_1d_rows_msa()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | max-literals.ll | 6 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
35 define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %r…
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
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| D | swizzle-export.ll | 9 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
11 %0 = extractelement <4 x float> %reg1, i32 0
12 %1 = extractelement <4 x float> %reg1, i32 1
13 %2 = extractelement <4 x float> %reg1, i32 2
14 %3 = extractelement <4 x float> %reg1, i32 3
99 define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
101 %0 = extractelement <4 x float> %reg1, i32 0
102 %1 = extractelement <4 x float> %reg1, i32 1
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| D | pv-packing.ll | 6 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
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| D | schedule-fs-loop-nested-if.ll | 4 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
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| D | r600cfg.ll | 3 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
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| D | rv7x0_count3.ll | 4 define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
6 %tmp = extractelement <4 x float> %reg1, i32 0
7 %tmp1 = extractelement <4 x float> %reg1, i32 1
8 %tmp2 = extractelement <4 x float> %reg1, i32 2
9 %tmp3 = extractelement <4 x float> %reg1, i32 3
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| D | load-input-fold.ll | 3 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
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| /external/libyuv/files/source/ |
| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); in I422ToRGB24Row_MSA()
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); in I422ToRGB24Row_MSA()
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
586 reg1 = (v8u16)__msa_srai_h(vec1, 4); in I422ToARGB4444Row_MSA()
588 reg1 = (v8u16)__msa_slli_h((v8i16)reg1, 4); in I422ToARGB4444Row_MSA()
590 reg1 |= const_0xF000; in I422ToARGB4444Row_MSA()
592 dst0 = (v16u8)(reg1 | reg0); in I422ToARGB4444Row_MSA()
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
626 reg1 = (v8u16)__msa_srai_h(vec1, 3); in I422ToARGB1555Row_MSA()
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
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| D | scale_msa.cc | 70 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
83 reg1 = __msa_hadd_u_h(vec1, vec1); in ScaleARGBRowDown2Box_MSA()
87 reg1 += reg3; in ScaleARGBRowDown2Box_MSA()
89 reg1 = (v8u16)__msa_srari_h((v8i16)reg1, 2); in ScaleARGBRowDown2Box_MSA()
90 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0); in ScaleARGBRowDown2Box_MSA()
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
158 reg1 = __msa_hadd_u_h(vec1, vec1); in ScaleARGBRowDownEvenBox_MSA()
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
296 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
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| /external/libavc/common/armv8/ |
| D | ih264_neon_macros.s | 36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
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| /external/libmpeg2/common/armv8/ |
| D | impeg2_neon_macros.s | 53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
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| /external/boringssl/src/crypto/perlasm/ |
| D | x86gas.pl | 77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
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| D | x86masm.pl | 46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
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| D | x86nasm.pl | 43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
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| /external/v8/src/compiler/mips64/ |
| D | code-generator-mips64.cc | 1040 Register reg1 = kScratchReg; in AssembleArchInstruction() local
1051 __ li(reg1, 0x1F); in AssembleArchInstruction()
1052 __ Subu(i.OutputRegister(), reg1, reg2); in AssembleArchInstruction()
1060 Register reg1 = kScratchReg; in AssembleArchInstruction() local
1071 __ li(reg1, 0x3F); in AssembleArchInstruction()
1072 __ Subu(i.OutputRegister(), reg1, reg2); in AssembleArchInstruction()
1080 Register reg1 = kScratchReg; in AssembleArchInstruction() local
1090 __ dsrl(reg1, i.InputRegister(0), 1); in AssembleArchInstruction()
1092 __ And(reg1, reg1, at); in AssembleArchInstruction()
1093 __ Daddu(reg1, reg1, reg2); in AssembleArchInstruction()
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| /external/mesa3d/src/util/ |
| D | register_allocate.c | 234 struct ra_reg *reg1 = ®s->regs[r1]; in ra_add_conflict_list() local
236 if (reg1->conflict_list) { in ra_add_conflict_list()
237 if (reg1->conflict_list_size == reg1->num_conflicts) { in ra_add_conflict_list()
238 reg1->conflict_list_size *= 2; in ra_add_conflict_list()
239 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list, in ra_add_conflict_list()
240 unsigned int, reg1->conflict_list_size); in ra_add_conflict_list()
242 reg1->conflict_list[reg1->num_conflicts++] = r2; in ra_add_conflict_list()
244 BITSET_SET(reg1->conflicts, r2); in ra_add_conflict_list()
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| /external/llvm/test/CodeGen/X86/ |
| D | copy-propagation.ll | 10 ; reg1 = copy reg2
12 ; reg2 = copy reg1
17 ; reg1 = copy reg2
20 ; reg2 = copy reg1
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| /external/libunwind/src/ptrace/ |
| D | _UPT_access_mem.c | 63 long reg1, reg2; in _UPT_access_mem()
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0); in _UPT_access_mem()
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1; in _UPT_access_mem()
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| /external/v8/src/compiler/mips/ |
| D | code-generator-mips.cc | 916 Register reg1 = kScratchReg; in AssembleArchInstruction() local
927 __ li(reg1, 0x1F); in AssembleArchInstruction()
928 __ Subu(i.OutputRegister(), reg1, reg2); in AssembleArchInstruction()
936 Register reg1 = kScratchReg; in AssembleArchInstruction() local
946 __ srl(reg1, i.InputRegister(0), 1); in AssembleArchInstruction()
948 __ And(reg1, reg1, at); in AssembleArchInstruction()
949 __ addu(reg1, reg1, reg2); in AssembleArchInstruction()
953 __ srl(reg2, reg1, 2); in AssembleArchInstruction()
955 __ And(reg1, reg1, at); in AssembleArchInstruction()
956 __ addu(reg1, reg1, reg2); in AssembleArchInstruction()
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 474 bool AreAliased(const CPURegister& reg1,
488 bool AreSameSizeAndType(const CPURegister& reg1,
501 bool AreSameFormat(const VRegister& reg1,
511 bool AreConsecutive(const VRegister& reg1,
520 explicit CPURegList(CPURegister reg1,
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
525 size_(reg1.GetSizeInBits()),
526 type_(reg1.GetType()) {
527 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
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| /external/aac/libFDK/include/ |
| D | fixpoint_math.h | 296 FIXP_DBL reg1, reg2; in invSqrtNorm2() local
319 reg1 = invSqrtTab[index] + (fMultDiv2(diff, Fract) << 1); in invSqrtNorm2()
327 reg1 = fMultAddDiv2(reg1, Fract, diff); in invSqrtNorm2()
341 reg1 = fMultDiv2(reg1, reg2) << 2; in invSqrtNorm2()
346 return (reg1); in invSqrtNorm2()
|