/external/libvpx/libvpx/vpx_dsp/mips/ |
D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local 48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store() 50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); in idct32x8_row_even_process_store() 52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store() 65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store() 66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); in idct32x8_row_even_process_store() 77 reg5 = reg7 + reg3; in idct32x8_row_even_process_store() 78 reg7 = reg7 - reg3; in idct32x8_row_even_process_store() 87 DOTP_CONST_PAIR(reg7, reg0, cospi_24_64, cospi_8_64, reg0, reg7); in idct32x8_row_even_process_store() 92 vec1 = reg7 - reg1; in idct32x8_row_even_process_store() [all …]
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D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local 19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa() 23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa() 24 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa() 41 DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3); in vpx_idct16_1d_rows_msa() 45 reg7 = reg15 - loc3; in vpx_idct16_1d_rows_msa() 65 DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9); in vpx_idct16_1d_rows_msa() 73 loc0 = reg7 + reg11; in vpx_idct16_1d_rows_msa() 74 reg11 = reg7 - reg11; in vpx_idct16_1d_rows_msa() 86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa() [all …]
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/external/libyuv/files/source/ |
D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local 109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA() 111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA() 131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA() 147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA() 148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA() 166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local 190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA() 192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA() 212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA() [all …]
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D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local 899 reg7 = reg1 * const_0x70; in ARGBToUVRow_MSA() 903 reg7 += const_0x8080; in ARGBToUVRow_MSA() 917 reg7 -= reg9; in ARGBToUVRow_MSA() 921 reg7 = (v8u16)__msa_srai_h((v8i16)reg7, 8); in ARGBToUVRow_MSA() 924 dst0 = (v16u8)__msa_pckev_b((v16i8)reg7, (v16i8)reg6); in ARGBToUVRow_MSA() 1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local 1267 reg7 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec7); in ARGBAttenuateRow_MSA() 1275 reg7 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec3); in ARGBAttenuateRow_MSA() 1283 reg7 = (v4u32)__msa_srai_w((v4i32)reg7, 24); in ARGBAttenuateRow_MSA() [all …]
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D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local 164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA() 166 reg5 += reg7; in ScaleARGBRowDownEvenBox_MSA()
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/external/llvm/test/CodeGen/AMDGPU/ |
D | pv.ll | 6 … x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) { 32 %24 = extractelement <4 x float> %reg7, i32 0 33 %25 = extractelement <4 x float> %reg7, i32 1 34 %26 = extractelement <4 x float> %reg7, i32 2 35 %27 = extractelement <4 x float> %reg7, i32 3
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D | big_alu.ll | 5 …eg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg … 49 %tmp42 = extractelement <4 x float> %reg7, i32 0 50 %tmp43 = extractelement <4 x float> %reg7, i32 1 51 %tmp44 = extractelement <4 x float> %reg7, i32 2 52 %tmp45 = extractelement <4 x float> %reg7, i32 3
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/external/vixl/src/aarch64/ |
D | operands-aarch64.h | 480 const CPURegister& reg7 = NoReg, 494 const CPURegister& reg7 = NoCPUReg,
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D | assembler-aarch64.cc | 4754 const CPURegister& reg7, in AreAliased() argument 4762 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased() 4793 const CPURegister& reg7, in AreSameSizeAndType() argument 4802 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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/external/v8/src/arm64/ |
D | assembler-arm64.cc | 230 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument 237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased() 267 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument 275 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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D | assembler-arm64.h | 361 const CPURegister& reg7 = NoReg, 374 const CPURegister& reg7 = NoCPUReg,
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/external/elfutils/tests/ |
D | run-addrcfi.sh | 40 integer reg7 (%edi): same_value 87 integer reg7 (%edi): same_value 139 integer reg7 (%rsp): location expression: call_frame_cfa stack_value 205 integer reg7 (%rsp): location expression: call_frame_cfa stack_value 309 integer reg7 (r7): undefined 1331 integer reg7 (r7): undefined 2359 integer reg7 (r7): undefined 3385 integer reg7 (%r7): same_value 3462 integer reg7 (%r7): same_value 3540 integer reg7 (r7): same_value [all …]
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/external/v8/src/x87/ |
D | macro-assembler-x87.cc | 2497 Register reg7, in AreAliased() argument 2501 reg7.is_valid() + reg8.is_valid(); in AreAliased() 2510 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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D | macro-assembler-x87.h | 53 Register reg6 = no_reg, Register reg7 = no_reg,
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/external/llvm/include/llvm/Support/ |
D | Dwarf.def | 208 HANDLE_DW_OP(0x57, reg7)
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/external/v8/src/ia32/ |
D | macro-assembler-ia32.cc | 2651 Register reg7, in AreAliased() argument 2655 reg7.is_valid() + reg8.is_valid(); in AreAliased() 2664 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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D | macro-assembler-ia32.h | 50 Register reg6 = no_reg, Register reg7 = no_reg,
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/external/v8/src/arm/ |
D | macro-assembler-arm.cc | 3741 Register reg7, in AreAliased() argument 3745 reg7.is_valid() + reg8.is_valid(); in AreAliased() 3754 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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D | macro-assembler-arm.h | 79 Register reg7 = no_reg,
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/external/elfutils/libdw/ |
D | known-dwarf.h | 527 DWARF_ONE_KNOWN_DW_OP (reg7, DW_OP_reg7) \
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/external/v8/src/ppc/ |
D | macro-assembler-ppc.cc | 4261 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument 4265 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased() 4275 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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/external/v8/src/s390/ |
D | macro-assembler-s390.cc | 5260 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument 5264 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased() 5274 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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/external/v8/src/x64/ |
D | macro-assembler-x64.cc | 5060 Register reg7, in AreAliased() argument 5064 reg7.is_valid() + reg8.is_valid(); in AreAliased() 5073 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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D | macro-assembler-x64.h | 74 Register reg7 = no_reg,
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/external/v8/src/mips/ |
D | macro-assembler-mips.cc | 6400 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument 6404 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased() 6414 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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