| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 1933 rorv x21,x20,x19 :: rd 8a258aa089fbe992 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000…
1934 rorv x21,x20,x19 :: rd 3c4ccf575655c875 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000…
1935 rorv x21,x20,x19 :: rd cbc174a3c6de6954 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000…
1936 rorv x21,x20,x19 :: rd 3b46c1131beed719 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000…
1937 rorv x21,x20,x19 :: rd 75f03d4a0adf164e rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000…
1938 rorv x21,x20,x19 :: rd d017f20c8c562e6d rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000…
1939 rorv x21,x20,x19 :: rd a3ce07c61eebad82 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000…
1940 rorv x21,x20,x19 :: rd b60a8f381f187bae rm b60a8f381f187bae, rn 008c208cc413ff00, cin 0, nzcv 00000…
1941 rorv x21,x20,x19 :: rd 5b05479c0f8c3dd7 rm b60a8f381f187bae, rn 008c208cc413ff01, cin 0, nzcv 00000…
1942 rorv x21,x20,x19 :: rd ad82a3ce07c61eeb rm b60a8f381f187bae, rn 008c208cc413ff02, cin 0, nzcv 00000…
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 16 ; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
103 ; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| D | arm64-regress-interphase-shift.ll | 13 ; CHECK: rorv
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-xfail-mips64r3.txt | 72 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-xfail-mips64r2.txt | 72 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-xfail-mips64r5.txt | 72 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-xfail-mips32r2.txt | 75 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-xfail-mips32r3.txt | 75 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-xfail-mips32r5.txt | 75 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 406 rorv w1, w2, w3
407 rorv x1, x2, x3
|
| D | basic-a64-instructions.s | 1526 rorv w0, w1, w2
1527 rorv x3, x4, x5
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 1057 rorv(rd, rn, rm); in Ror()
|
| D | assembler-arm64.h | 1125 void rorv(const Register& rd, const Register& rn, const Register& rm);
|
| D | assembler-arm64.cc | 1276 void Assembler::rorv(const Register& rd, in rorv() function in v8::internal::Assembler
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 681 void rorv(const Register& rd, const Register& rn, const Register& rm);
|
| D | macro-assembler-aarch64.h | 1776 rorv(rd, rn, rm); in Ror()
|
| D | assembler-aarch64.cc | 581 void Assembler::rorv(const Register& rd, in rorv() function in vixl::aarch64::Assembler
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 277 __ rorv(w26, w27, w28); in GenerateTestSequenceBase() local
278 __ rorv(x29, x2, x3); in GenerateTestSequenceBase() local
|
| D | test-disasm-aarch64.cc | 920 COMPARE(rorv(w18, w19, w20), "ror w18, w19, w20"); in TEST()
921 COMPARE(rorv(x21, x22, x23), "ror x21, x22, x23"); in TEST()
|
| D | test-assembler-aarch64.cc | 9600 TEST(rorv) { in TEST() argument
9618 __ rorv(x0, x0, xzr); in TEST() local
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 973 void rorv(const Register& rd, const Register& rn, const Register& rm)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 713 def : ShiftAlias<"rorv", RORVWr, GPR32>;
714 def : ShiftAlias<"rorv", RORVXr, GPR64>;
|