| /external/llvm/test/CodeGen/AArch64/ |
| D | fast-isel-tbz.ll | 66 ; CHECK: tbnz w0, #0, {{LBB.+_2}}
78 ; CHECK: tbnz w0, #1, {{LBB.+_2}}
90 ; CHECK: tbnz w0, #2, {{LBB.+_2}}
102 ; CHECK: tbnz w0, #3, {{LBB.+_2}}
114 ; CHECK: tbnz x0, #32, {{LBB.+_2}}
126 ; FAST: tbnz w0, #7, {{LBB.+_2}}
137 ; FAST: tbnz w0, #15, {{LBB.+_2}}
148 ; CHECK: tbnz w0, #31, {{LBB.+_2}}
159 ; CHECK: tbnz x0, #63, {{LBB.+_2}}
192 ; FAST: tbnz w0, #7, {{LBB.+_2}}
[all …]
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| D | tbz-tbnz.ll | 49 ; CHECK: tbnz [[CMP]], #31
67 ; CHECK: tbnz [[CMP]], #63
85 ; CHECK: tbnz [[CMP]], #31
103 ; CHECK: tbnz [[CMP]], #63
147 ; CHECK: tbnz [[CMP]], #63
265 ; CHECK: tbnz w0, #0
281 ; CHECK: tbnz w0, #0
299 ; CHECK: tbnz w0, #2
317 ; CHECK: tbnz w0, #3
334 ; CHECK: tbnz w0, #31
[all …]
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| D | optimize-cond-branch.ll | 5 ; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
14 ; CHECK: tbnz
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| D | analyze-branch.ll | 149 ; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
216 ; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
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| D | branch-relax-asm.ll | 5 ; It would be more natural to use just one "tbnz %false" here, but if the
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| D | fast-isel-branch-cond-split.ll | 47 ; CHECK-NEXT: tbnz w8, #0,
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| D | cxx-tlscc.ll | 57 ; CHECK: tbnz w{{.*}}, #0, [[BB_end:.?LBB0_[0-9]+]]
104 ; CHECK-O0: tbnz w{{.*}}, #0, [[BB_end:.?LBB0_[0-9]+]]
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-branch-encoding.s | 115 tbnz x1, #63, foo
120 tbnz w1, #31, foo
127 tbnz x3, #8, #-32768
128 ; CHECK: tbnz w3, #8, #-32768 ; encoding: [0x03,0x00,0x44,0x37]
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| D | elf-reloc-tstb.s | 5 tbnz w3, #15, somewhere
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| D | basic-a64-diagnostics.s | 3745 tbnz w3, #-1, addr
3746 tbnz w3, #32, nowhere
3747 tbnz x9, #-1, there
3748 tbnz x20, #64, dont
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| D | basic-a64-instructions.s | 4833 tbnz x5, #45, nowhere
4843 tbnz w3, #2, there
4844 tbnz wzr, #31, nowhere
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-branch.txt | 20 # CHECK: tbnz w11, #3, #0
58 # CHECK: tbnz w0, #1, #12
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| D | basic-a64-instructions.txt | 4305 # CHECK: tbnz x12, #60, #32764
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| /external/v8/src/ic/arm64/ |
| D | ic-arm64.cc | 93 patcher.tbnz(smi_reg, 0, branch_imm); in PatchInlinedSmiCode()
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| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1007 void tbnz(const Register& rt, unsigned bit_pos, Label* label);
1008 void tbnz(const Register& rt, unsigned bit_pos, int imm14);
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| D | assembler-arm64.cc | 1067 void Assembler::tbnz(const Register& rt, in tbnz() function in v8::internal::Assembler
1075 void Assembler::tbnz(const Register& rt, in tbnz() function in v8::internal::Assembler
1078 tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); in tbnz()
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| D | macro-assembler-arm64.cc | 782 tbnz(rt, bit_pos, label); in Tbnz()
796 tbnz(rt, bit_pos, &done); in Tbz()
1342 tbnz(StackPointer(), kXSignBit, &ok); // Ok if csp < StackPointer(). in AssertStackConsistency()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 685 tbnz(rt, bit_pos, label); in Tbnz()
701 tbnz(rt, bit_pos, &done); in Tbz()
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| D | assembler-aarch64.h | 579 void tbnz(const Register& rt, unsigned bit_pos, Label* label);
582 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14);
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| D | assembler-aarch64.cc | 364 void Assembler::tbnz(const Register& rt, unsigned bit_pos, int64_t imm14) { in tbnz() function in vixl::aarch64::Assembler
370 void Assembler::tbnz(const Register& rt, unsigned bit_pos, Label* label) { in tbnz() function in vixl::aarch64::Assembler
373 tbnz(rt, bit_pos, static_cast<int>(offset)); in tbnz()
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| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 984 COMPARE_PREFIX(tbnz(w8, 0, INST_OFF(0x7ffc)), "tbnz w8, #0, #+0x7ffc"); in TEST()
985 COMPARE_PREFIX(tbnz(x9, 63, INST_OFF(-0x8000)), "tbnz x9, #63, #-0x8000"); in TEST()
986 COMPARE_PREFIX(tbnz(w10, 31, INST_OFF(0)), "tbnz w10, #31, #+0x0"); in TEST()
987 COMPARE_PREFIX(tbnz(x11, 31, INST_OFF(0x4)), "tbnz w11, #31, #+0x4"); in TEST()
988 COMPARE_PREFIX(tbnz(x12, 32, INST_OFF(0x8)), "tbnz x12, #32, #+0x8"); in TEST()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1276 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14)
1283 void tbnz(const Register& rt, unsigned bit_pos, Label* label)
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| /external/v8/src/full-codegen/arm64/ |
| D | full-codegen-arm64.cc | 63 __ tbnz(xzr, 0, target); // Never taken before patched. in EmitJumpIfSmi() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1258 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
|