Searched refs:v256i8 (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 76 v256i8 = 29, //256 x i8 enumerator
279 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
333 case v256i8: return i8; in getVectorElementType()
377 case v256i8: return 256; in getVectorNumElements()
508 case v256i8: in getSizeInBits()
611 if (NumElements == 256) return MVT::v256i8; in getVectorVT()
|
| D | ValueTypes.td | 53 def v256i8 : ValueType<2048,29>; //256 x i8 vector value
|
| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 161 case MVT::v256i8: return "v256i8"; in getEVTString()
239 case MVT::v256i8: return VectorType::get(Type::getInt8Ty(Context), 256); in getTypeForEVT()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 210 LocVT == MVT::v256i8) { in CC_Hexagon_VarArg()
361 LocVT == MVT::v256i8)) { in CC_HexagonVector()
424 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || in RetCC_Hexagon()
548 ty == MVT::v256i8 || in IsHvxVectorType()
1141 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { in LowerFormalArguments()
1769 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2004 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); in HexagonTargetLowering()
2896 case MVT::v256i8: in getRegForInlineAsmConstraint()
3030 case MVT::v256i8: in allowsMisalignedMemoryAccesses()
3071 case MVT::v256i8: in findRepresentativeClass()
|
| D | HexagonRegisterInfo.td | 238 [v256i8,v128i16,v64i32,v32i64], 2048,
|
| D | HexagonInstrInfoV60.td | 798 defm : STrivv_pats <v128i8, v256i8>;
873 defm : LDrivv_pats <v128i8, v256i8>;
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 89 case MVT::v256i8: return "MVT::v256i8"; in getEnumName()
|
| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 186 def llvm_v256i8_ty : LLVMType<v256i8>; //256 x i8
|