Home
last modified time | relevance | path

Searched refs:v4i64 (Results 1 – 25 of 70) sorted by relevance

123

/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
159 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
200 { ISD::SHL, MVT::v4i64, 2 }, in getArithmeticInstrCost()
201 { ISD::SRL, MVT::v4i64, 4 }, in getArithmeticInstrCost()
202 { ISD::SRA, MVT::v4i64, 4 }, in getArithmeticInstrCost()
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
227 { ISD::SDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
231 { ISD::UDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
253 { ISD::SHL, MVT::v4i64, 2 }, // psllq. in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
420 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
421 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
422 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
424 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
425 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
430 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
DX86InstrFragmentsSIMD.td616 // NOTE: all 256-bit integer vector loads are promoted to v4i64
619 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
691 // NOTE: all 256-bit integer vector loads are promoted to v4i64
697 (v4i64 (alignedload256 node:$ptr))>;
774 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
775 Mgt->getBasePtr().getValueType() == MVT::v4i64);
812 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
813 Sc->getBasePtr().getValueType() == MVT::v4i64);
852 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h68 v4i64 = 26, // 4 x i64 enumerator
204 case v4i64: in getVectorElementType()
229 case v4i64: in getVectorNumElements()
281 case v4i64: in getSizeInBits()
359 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
505 V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64); in is256BitVector()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h97 v4i64 = 47, // 4 x i64 enumerator
259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
351 case v4i64: in getVectorElementType()
407 case v4i64: in getVectorNumElements()
493 case v4i64: in getSizeInBits()
635 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
449 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll11 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
39 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Davx-cmp.ll61 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
105 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Dfold-vector-sext-crash.ll6 ; due to an illegal build_vector of type MVT::v4i64.
Dvector-popcnt-256.ll42 %out = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %in)
185 %out = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> <i64 256, i64 -1, i64 0, i64 255>)
216 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>)
Dbswap-vector.ll117 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
248 %r = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
349 %bs1 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
350 %bs2 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %bs1)
487 %r = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> <i64 255, i64 -1, i64 65535, i64 16776960>)
Davx2-arith.ll106 ; CHECK: mul-v4i64
116 define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll15 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>)
34 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)
99 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1)
127 %ctlz = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 0)
136 %ctlz = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 1)
255 declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)
283 %cttz = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 0)
292 %cttz = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 1)
Dbswap.ll14 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
36 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
/external/llvm/test/CodeGen/AMDGPU/
Dctpop64.ll6 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
78 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
110 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
Dbswap.ll10 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
112 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp134 case MVT::v4i64: return "v4i64"; in getEVTString()
181 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4); in getTypeForEVT()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CallingConv.td46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
162 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
178 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
277 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
285 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrFragmentsSIMD.td218 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
265 (v4i64 (alignedload256 node:$ptr))>;
293 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
341 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
DX86GenDAGISel.inc5737 /*12606*/ OPC_CheckChild1Type, MVT::v4i64,
5748 …// Src: (st VR256:v4i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<…
5749 // Dst: (VMOVAPSYmr addr:iPTR:$dst, VR256:v4i64:$src)
5756 …// Src: (st VR256:v4i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> -…
5757 // Dst: (VMOVUPSYmr addr:iPTR:$dst, VR256:v4i64:$src)
6196 /*13585*/ OPC_CheckType, MVT::v4i64,
6203 1/*#VTs*/, MVT::v4i64, 3/*#Ops*/, 1, 2, 3,
6204 …// Src: (X86vzmovl:v4i64 (insert_subvector:v4i64 (undef:v4i64), (scalar_to_vector:v2i64 GR64:i64:$…
6205 … // Dst: (SUBREG_TO_REG:v4i64 0:i64, (VMOVZQI2PQIrr:v16i8 GR64:i64:$src), sub_xmm:i32)
21818 …// Src: (intrinsic_wo_chain:v4f64 186:iPTR, VR256:v4f64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predi…
[all …]
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp109 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
113 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
114 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
301 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Davx-cmp.ll61 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
105 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
/external/llvm/test/CodeGen/AArch64/
Daarch64-vcvtfp2fxs-combine.ll6 ; with a v4f64 input. Since v4i64 is not legal we should bail out. We can
/external/llvm/lib/IR/
DValueTypes.cpp179 case MVT::v4i64: return "v4i64"; in getEVTString()
257 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4); in getTypeForEVT()

123