Searched refs:vgpr (Results 1 – 14 of 14) sorted by relevance
/external/clang/test/Sema/ |
D | inline-asm-validate-amdgpu.cl | 7 int sgpr = 0, vgpr = 0, imm = 0; 12 // vgpr constraints 13 __asm__ ("v_mov_b32 %0, %1" : "=v" (vgpr) : "v" (imm) : );
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/external/llvm/test/CodeGen/AMDGPU/ |
D | smrd-vccz-bug.ll | 39 %vgpr = load volatile float, float addrspace(1)* %in 40 %cnd = fcmp oeq float 0.0, %vgpr 44 store float %vgpr, float addrspace(1)* %out
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D | vop-shrink.ll | 13 %vgpr = call i32 @llvm.amdgcn.workitem.id.x() #1 25 %tmp4 = sub i32 %vgpr, %tmp3
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D | local-stack-slot-bug.ll | 1 ; RUN: llc -march=amdgcn -mcpu=verde -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck %s
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D | write-register-vgpr-into-sgpr.ll | 6 ; vgpr value into a scalar register, but I don't think there's much we
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D | skip-if-dead.ll | 243 %vgpr = load volatile i32, i32 addrspace(1)* undef 244 %loop.cond = icmp eq i32 %vgpr, 0
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D | madak.ll | 214 %vgpr = load volatile float, float addrspace(1)* undef 217 %tmp2 = fmul float %tmp1, %vgpr
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D | ret.ll | 6 ; GCN-LABEL: {{^}}vgpr: 12 define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, fl…
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D | vgpr-spill-emergency-stack-slot-compute.ll | 1 ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck … 2 ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -c… 3 ; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-… 4 ; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-ma…
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D | llvm.amdgcn.buffer.atomic.ll | 68 ; first vgpr. Since we don't do that yet, the register allocator will have to
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D | vgpr-spill-emergency-stack-slot.ll | 1 ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck … 2 ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -c…
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D | and.ll | 72 ; Just to stop future replacement of copy to vgpr + store with VALU op.
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_shader.c | 2801 unsigned vgpr; in si_llvm_emit_tcs_epilogue() local 2826 vgpr = SI_TCS_NUM_USER_SGPR + 2; in si_llvm_emit_tcs_epilogue() 2827 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, ""); in si_llvm_emit_tcs_epilogue() 2828 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, ""); in si_llvm_emit_tcs_epilogue() 2829 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, ""); in si_llvm_emit_tcs_epilogue() 3206 unsigned i, j, first_vgpr, vgpr; in si_llvm_return_fs_outputs() local 3255 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1; in si_llvm_return_fs_outputs() 3261 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, ""); in si_llvm_return_fs_outputs() 3264 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, ""); in si_llvm_return_fs_outputs() 3266 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, ""); in si_llvm_return_fs_outputs() [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPU.td | 207 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
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