| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| D | vsqrt.ll | 1 ; Show that we can translate intrinsic vsqrt into a binary instruction.
33 ; ASM: vsqrt.f32 s20, s20
35 ; IASM-NOT: vsqrt.f32
47 ; ASM: vsqrt.f64 d20, d20
49 ; IASM-NOT: vsqrt.f64
|
| /external/llvm/test/MC/ARM/ |
| D | single-precision-fp.s | 47 vsqrt.f64 d13, d12
48 vsqrt d13, d14
52 @ CHECK-ERRORS-NEXT: vsqrt.f64 d13, d12
54 @ CHECK-ERRORS-NEXT: vsqrt d13, d14
|
| D | simple-fp-encoding.s | 71 vsqrt.f64 d16, d16
72 vsqrt.f32 s0, s0
74 @ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
75 @ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
|
| D | fullfp16.s | 64 vsqrt.f16 s0, s0
65 @ ARM: vsqrt.f16 s0, s0 @ encoding: [0xc0,0x09,0xb1,0xee]
66 @ THUMB: vsqrt.f16 s0, s0 @ encoding: [0xb1,0xee,0xc0,0x09]
|
| D | fullfp16-neg.s | 49 vsqrt.f16 s0, s0
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | simple-fp-encoding.s | 63 @ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
64 vsqrt.f64 d16, d16
66 @ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
67 vsqrt.f32 s0, s0
|
| /external/llvm/test/CodeGen/ARM/ |
| D | 2011-11-29-128bitArithmetics.ll | 12 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
13 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
14 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
15 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
|
| D | fp16-promote.ll | 422 ; CHECK-FP16: vsqrt.f32
425 ; CHECK-VFP-LIBCALL: vsqrt.f32
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | nacl-other-intrinsics.ll | 177 ; ARM32: vsqrt.f32
178 ; ARM32: vsqrt.f32
179 ; ARM32: vsqrt.f32
202 ; ARM32: vsqrt.f32
217 ; ARM32: vsqrt.f64
218 ; ARM32: vsqrt.f64
219 ; ARM32: vsqrt.f64
239 ; ARM32: vsqrt.f64
|
| /external/capstone/suite/MC/ARM/ |
| D | simple-fp-encoding.s.cs | 26 0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16
27 0xc0,0x0a,0xb1,0xee = vsqrt.f32 s0, s0
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 58 # CHECK: vsqrt.f64 d16, d16
61 # CHECK: vsqrt.f32 s0, s0
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 58 # CHECK: vsqrt.f64 d16, d16
61 # CHECK: vsqrt.f32 s0, s0
|
| D | fullfp16-arm.txt | 48 # CHECK: vsqrt.f16 s0, s0
|
| D | fullfp16-thumb.txt | 48 # CHECK: vsqrt.f16 s0, s0
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | float-intrinsics-float.ll | 12 ; HARD: vsqrt.f32 s0, s0
|
| D | float-intrinsics-double.ll | 12 ; HARD: vsqrt.f64 d0, d0
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 948 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
953 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
958 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
2209 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
2210 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
2262 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2263 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
|
| /external/v8/src/compiler/arm/ |
| D | code-generator-arm.cc | 152 __ vsqrt(result_, result_); in Generate() local
167 __ vsqrt(result_, result_); in Generate() local
1151 __ vsqrt(i.OutputFloatRegister(), i.InputFloatRegister(0)); in AssembleArchInstruction() local
1216 __ vsqrt(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); in AssembleArchInstruction() local
|
| /external/v8/src/arm/ |
| D | codegen-arm.cc | 281 __ vsqrt(d0, d0); in CreateSqrtFunction()
|
| D | assembler-arm.h | 1311 void vsqrt(const DwVfpRegister dst,
1314 void vsqrt(const SwVfpRegister dst, const SwVfpRegister src,
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| D | assembler-arm.cc | 3655 void Assembler::vsqrt(const DwVfpRegister dst, in vsqrt() function in v8::internal::Assembler
3672 void Assembler::vsqrt(const SwVfpRegister dst, const SwVfpRegister src, in vsqrt() function in v8::internal::Assembler
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 442 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
447 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5756 void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm);
5757 void vsqrt(DataType dt, SRegister rd, SRegister rm) { vsqrt(al, dt, rd, rm); } in vsqrt() function
5759 void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm);
5760 void vsqrt(DataType dt, DRegister rd, DRegister rm) { vsqrt(al, dt, rd, rm); } in vsqrt() function
|
| D | disasm-aarch32.h | 2479 void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm);
2481 void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm);
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrSSE.td | 2972 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2973 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
2975 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2976 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2977 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2978 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2979 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2980 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2981 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2982 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
|