| /hardware/google/av/codec2/include/ |
| D | _C2MacroUtils.h | 80 #define _C2_MAP_64(fn, arg, head, ...) fn(head, arg), _C2_MAP_63(fn, arg, ##__VA_ARGS__) argument
81 #define _C2_MAP_63(fn, arg, head, ...) fn(head, arg), _C2_MAP_62(fn, arg, ##__VA_ARGS__) argument
82 #define _C2_MAP_62(fn, arg, head, ...) fn(head, arg), _C2_MAP_61(fn, arg, ##__VA_ARGS__) argument
83 #define _C2_MAP_61(fn, arg, head, ...) fn(head, arg), _C2_MAP_60(fn, arg, ##__VA_ARGS__) argument
84 #define _C2_MAP_60(fn, arg, head, ...) fn(head, arg), _C2_MAP_59(fn, arg, ##__VA_ARGS__) argument
85 #define _C2_MAP_59(fn, arg, head, ...) fn(head, arg), _C2_MAP_58(fn, arg, ##__VA_ARGS__) argument
86 #define _C2_MAP_58(fn, arg, head, ...) fn(head, arg), _C2_MAP_57(fn, arg, ##__VA_ARGS__) argument
87 #define _C2_MAP_57(fn, arg, head, ...) fn(head, arg), _C2_MAP_56(fn, arg, ##__VA_ARGS__) argument
88 #define _C2_MAP_56(fn, arg, head, ...) fn(head, arg), _C2_MAP_55(fn, arg, ##__VA_ARGS__) argument
89 #define _C2_MAP_55(fn, arg, head, ...) fn(head, arg), _C2_MAP_54(fn, arg, ##__VA_ARGS__) argument
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| /hardware/interfaces/configstore/1.0/vts/functional/ |
| D | VtsHalConfigstoreV1_0TargetTest.cpp | 70 [&tmp](OptionalInt64 arg) { tmp = arg.specified; }); in TEST_F() argument
74 [&tmp](OptionalInt64 arg) { tmp = arg.specified; }); in TEST_F() argument
78 [&tmp](OptionalBool arg) { tmp = arg.specified; }); in TEST_F() argument
82 [&tmp](OptionalBool arg) { tmp = arg.specified; }); in TEST_F() argument
86 [&tmp](OptionalBool arg) { tmp = arg.specified; }); in TEST_F() argument
90 [&tmp](OptionalInt64 arg) { tmp = arg.specified; }); in TEST_F() argument
94 [&tmp](OptionalBool arg) { tmp = arg.specified; }); in TEST_F() argument
98 [&tmp](OptionalUInt64 arg) { tmp = arg.specified; }); in TEST_F() argument
102 [&tmp](OptionalBool arg) { tmp = arg.specified; }); in TEST_F() argument
106 [&tmp](OptionalBool arg) { tmp = arg.specified; }); in TEST_F() argument
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/ |
| D | VsyncControl.cpp | 50 struct drm_psb_vsync_set_arg arg; in control() local
51 memset(&arg, 0, sizeof(struct drm_psb_vsync_set_arg)); in control()
54 arg.vsync.pipe = disp; in control()
57 arg.vsync_operation_mask = VSYNC_ENABLE; in control()
59 arg.vsync_operation_mask = VSYNC_DISABLE; in control()
62 return drm->writeReadIoctl(DRM_PSB_VSYNC_SET, &arg, sizeof(arg)); in control()
69 struct drm_psb_vsync_set_arg arg; in wait() local
70 memset(&arg, 0, sizeof(struct drm_psb_vsync_set_arg)); in wait()
72 arg.vsync_operation_mask = VSYNC_WAIT; in wait()
75 arg.vsync.pipe = disp; in wait()
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| D | WsbmWrapper.c | 33 struct psb_validate_arg arg; member
36 static inline uint32_t align_to(uint32_t arg, uint32_t align) in align_to() argument
38 return ((arg + (align - 1)) & (~(align - 1))); in align_to()
84 memset(&vNode->arg.d.req, 0, sizeof(vNode->arg.d.req)); in pvrClear()
110 union drm_psb_extension_arg arg; in psbWsbmInitialize() local
131 strncpy(arg.extension, drmExt, sizeof(drmExt)); in psbWsbmInitialize()
133 ret = drmCommandWriteRead(drmFD, 6/*DRM_PSB_EXTENSION*/, &arg, sizeof(arg)); in psbWsbmInitialize()
134 if(ret || !arg.rep.exists) { in psbWsbmInitialize()
139 unsigned int ioctl_offset = arg.rep.driver_ioctl_offset; in psbWsbmInitialize()
142 mainPool = wsbmTTMPoolInit(drmFD, arg.rep.driver_ioctl_offset); in psbWsbmInitialize()
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| /hardware/intel/common/libwsbm/src/ |
| D | wsbm_ttmpool.c | 118 union ttm_pl_create_arg arg; in pool_create() local
134 arg.req.size = size; in pool_create()
135 arg.req.placement = placement; in pool_create()
136 arg.req.page_alignment = alignment / pageSize; in pool_create()
139 arg, ret); in pool_create()
145 dBuf->kBuf.gpuOffset = arg.rep.gpu_offset; in pool_create()
146 dBuf->mapHandle = arg.rep.map_handle; in pool_create()
147 dBuf->realSize = arg.rep.bo_size; in pool_create()
148 dBuf->kBuf.placement = arg.rep.placement; in pool_create()
149 dBuf->kBuf.handle = arg.rep.handle; in pool_create()
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| D | wsbm_slabpool.c | 223 wsbmTimeAdd(struct timeval *arg, struct timeval *add) in wsbmTimeAdd() argument
227 arg->tv_sec += add->tv_sec; in wsbmTimeAdd()
228 arg->tv_usec += add->tv_usec; in wsbmTimeAdd()
229 sec = arg->tv_usec / 1000000; in wsbmTimeAdd()
230 arg->tv_sec += sec; in wsbmTimeAdd()
231 arg->tv_usec -= sec * 1000000; in wsbmTimeAdd()
237 struct ttm_pl_reference_req arg; in wsbmFreeKernelBO() local
244 arg.handle = kbo->kBuf.handle; in wsbmFreeKernelBO()
247 slabPool->devOffset + TTM_PL_UNREF, &arg, in wsbmFreeKernelBO()
248 sizeof(arg)); in wsbmFreeKernelBO()
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| D | wsbm_fencemgr.c | 364 union ttm_fence_signaled_arg arg; in tSignaled() local
367 arg.req.handle = (unsigned long)private; in tSignaled()
368 arg.req.fence_type = flush_type; in tSignaled()
369 arg.req.flush = 1; in tSignaled()
373 &arg, sizeof(arg)); in tSignaled()
377 *signaled_type = arg.rep.signaled_types; in tSignaled()
387 union ttm_fence_finish_arg arg = in tFinish() local
396 &arg, sizeof(arg)); in tFinish()
407 struct ttm_fence_unref_arg arg = {.handle = (unsigned long)*private }; in tUnref() local
412 &arg, sizeof(arg)); in tUnref()
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| /hardware/intel/img/hwcomposer/merrifield/ips/anniedale/ |
| D | AnnCursorPlane.cpp | 170 struct drm_psb_register_rw_arg arg; in enablePlane() local
171 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
173 arg.plane_enable_mask = 1; in enablePlane()
175 arg.plane_disable_mask = 1; in enablePlane()
178 arg.plane.type = DC_CURSOR_PLANE; in enablePlane()
179 arg.plane.index = mIndex; in enablePlane()
180 arg.plane.ctx = 0; in enablePlane()
184 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
197 struct drm_psb_register_rw_arg arg; in isDisabled() local
198 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in isDisabled()
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| D | AnnRGBPlane.cpp | 201 struct drm_psb_register_rw_arg arg; in enablePlane() local
202 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
204 arg.plane_enable_mask = 1; in enablePlane()
206 arg.plane_disable_mask = 1; in enablePlane()
210 arg.plane.type = DC_SPRITE_PLANE; in enablePlane()
212 arg.plane.type = DC_PRIMARY_PLANE; in enablePlane()
214 arg.plane.index = mIndex; in enablePlane()
215 arg.plane.ctx = 0; in enablePlane()
219 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
232 struct drm_psb_register_rw_arg arg; in isDisabled() local
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/anniedale/ |
| D | AnnCursorPlane.cpp | 191 struct drm_psb_register_rw_arg arg; in enablePlane() local
192 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
194 arg.plane_enable_mask = 1; in enablePlane()
196 arg.plane_disable_mask = 1; in enablePlane()
199 arg.plane.type = DC_CURSOR_PLANE; in enablePlane()
200 arg.plane.index = mIndex; in enablePlane()
201 arg.plane.ctx = 0; in enablePlane()
205 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
218 struct drm_psb_register_rw_arg arg; in isDisabled() local
219 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in isDisabled()
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| D | AnnRGBPlane.cpp | 259 struct drm_psb_register_rw_arg arg; in enablePlane() local
260 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
262 arg.plane_enable_mask = 1; in enablePlane()
264 arg.plane_disable_mask = 1; in enablePlane()
268 arg.plane.type = DC_SPRITE_PLANE; in enablePlane()
270 arg.plane.type = DC_PRIMARY_PLANE; in enablePlane()
272 arg.plane.index = mIndex; in enablePlane()
273 arg.plane.ctx = 0; in enablePlane()
277 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
290 struct drm_psb_register_rw_arg arg; in isDisabled() local
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| /hardware/intel/img/hwcomposer/merrifield/ips/tangier/ |
| D | TngCursorPlane.cpp | 193 struct drm_psb_register_rw_arg arg; in enablePlane() local
194 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
196 arg.plane_enable_mask = 1; in enablePlane()
198 arg.plane_disable_mask = 1; in enablePlane()
201 arg.plane.type = DC_CURSOR_PLANE; in enablePlane()
202 arg.plane.index = mIndex; in enablePlane()
203 arg.plane.ctx = 0; in enablePlane()
207 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
220 struct drm_psb_register_rw_arg arg; in isDisabled() local
221 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in isDisabled()
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| D | TngSpritePlane.cpp | 131 struct drm_psb_register_rw_arg arg; in enablePlane() local
132 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
134 arg.plane_enable_mask = 1; in enablePlane()
136 arg.plane_disable_mask = 1; in enablePlane()
138 arg.plane.type = DC_SPRITE_PLANE; in enablePlane()
139 arg.plane.index = mIndex; in enablePlane()
140 arg.plane.ctx = 0; in enablePlane()
144 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
166 struct drm_psb_register_rw_arg arg; in isDisabled() local
167 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in isDisabled()
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| D | TngGrallocBufferMapper.cpp | 62 struct psb_gtt_mapping_arg arg; in gttMap() local
72 arg.type = PSB_GTT_MAP_TYPE_VIRTUAL; in gttMap()
73 arg.page_align = gttAlign; in gttMap()
74 arg.vaddr = (unsigned long)vaddr; in gttMap()
75 arg.size = size; in gttMap()
78 ret = drm->writeReadIoctl(DRM_PSB_GTT_MAP, &arg, sizeof(arg)); in gttMap()
84 VTRACE("offset = %#x", arg.offset_pages); in gttMap()
85 *offset = arg.offset_pages; in gttMap()
91 struct psb_gtt_mapping_arg arg; in gttUnmap() local
101 arg.type = PSB_GTT_MAP_TYPE_VIRTUAL; in gttUnmap()
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| D | TngOverlayPlane.cpp | 188 struct drm_psb_register_rw_arg arg; in flush() local
189 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in flush()
192 arg.plane_disable_mask = 1; in flush()
194 arg.plane_enable_mask = 1; in flush()
196 arg.plane.type = DC_OVERLAY_PLANE; in flush()
197 arg.plane.index = mIndex; in flush()
198 arg.plane.ctx = (mBackBuffer[mCurrent]->gttOffsetInPage << 12); in flush()
200 arg.plane.ctx |= mPipeConfig; in flush()
208 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in flush()
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| D | TngPrimaryPlane.cpp | 83 struct drm_psb_register_rw_arg arg; in enablePlane() local
84 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg)); in enablePlane()
86 arg.plane_enable_mask = 1; in enablePlane()
88 arg.plane_disable_mask = 1; in enablePlane()
90 arg.plane.type = DC_PRIMARY_PLANE; in enablePlane()
91 arg.plane.index = mIndex; in enablePlane()
92 arg.plane.ctx = 0; in enablePlane()
96 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/tangier/ |
| D | TngGrallocBufferMapper.cpp | 62 struct psb_gtt_mapping_arg arg; in gttMap() local
72 arg.type = PSB_GTT_MAP_TYPE_VIRTUAL; in gttMap()
73 arg.page_align = gttAlign; in gttMap()
74 arg.vaddr = (uint32_t)vaddr; in gttMap()
75 arg.size = size; in gttMap()
78 ret = drm->writeReadIoctl(DRM_PSB_GTT_MAP, &arg, sizeof(arg)); in gttMap()
84 VLOGTRACE("offset = %#x", arg.offset_pages); in gttMap()
85 *offset = arg.offset_pages; in gttMap()
91 struct psb_gtt_mapping_arg arg; in gttUnmap() local
101 arg.type = PSB_GTT_MAP_TYPE_VIRTUAL; in gttUnmap()
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| /hardware/nxp/secure_element/libese-spi/p73/spm/ |
| D | phNxpEse_Spm.cpp | 94 ESESTATUS phNxpEse_SPM_ConfigPwr(spm_power_t arg) { in phNxpEse_SPM_ConfigPwr() argument
99 ret = phPalEse_ioctl(phPalEse_e_ChipRst, pEseDeviceHandle, arg); in phNxpEse_SPM_ConfigPwr()
100 switch (arg) { in phNxpEse_SPM_ConfigPwr()
251 ESESTATUS phNxpEse_SPM_SetPwrScheme(long arg) { in phNxpEse_SPM_SetPwrScheme() argument
256 __FUNCTION__, arg); in phNxpEse_SPM_SetPwrScheme()
257 ret = phPalEse_ioctl(phPalEse_e_SetPowerScheme, pEseDeviceHandle, arg); in phNxpEse_SPM_SetPwrScheme()
275 ESESTATUS phNxpEse_SPM_DisablePwrControl(unsigned long arg) { in phNxpEse_SPM_DisablePwrControl() argument
280 __FUNCTION__, arg); in phNxpEse_SPM_DisablePwrControl()
281 ret = phPalEse_ioctl(phPalEse_e_DisablePwrCntrl, pEseDeviceHandle, arg); in phNxpEse_SPM_DisablePwrControl()
327 ESESTATUS phNxpEse_SPM_SetJcopDwnldState(long arg) { in phNxpEse_SPM_SetJcopDwnldState() argument
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| D | phNxpEse_Spm.h | 56 ESESTATUS phNxpEse_SPM_ConfigPwr(spm_power_t arg);
65 ESESTATUS phNxpEse_SPM_SetState(long arg);
70 ESESTATUS phNxpEse_SPM_SetPwrScheme(long arg);
72 ESESTATUS phNxpEse_SPM_DisablePwrControl(unsigned long arg);
74 ESESTATUS phNxpEse_SPM_SetJcopDwnldState(long arg);
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| /hardware/interfaces/gnss/1.0/default/ |
| D | ThreadCreationWrapper.h | 33 ThreadFuncArgs(void (*start)(void*), void* arg) : fptr(start), args(arg) {} in ThreadFuncArgs()
46 void* threadFunc(void* arg);
55 pthread_t createPthread(const char* name, void (*start)(void*), void* arg,
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| D | ThreadCreationWrapper.cpp | 19 void* threadFunc(void* arg) { in threadFunc() argument
20 ThreadFuncArgs* threadArgs = reinterpret_cast<ThreadFuncArgs*>(arg); in threadFunc()
27 void* arg, std::vector<std::unique_ptr<ThreadFuncArgs>> * listArgs) { in createPthread() argument
29 auto threadArgs = new ThreadFuncArgs(start, arg); in createPthread()
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| /hardware/broadcom/wlan/bcmdhd/dhdutil/ |
| D | dhdu_nl80211.c | 38 static int dhd_nl_error_handler(struct sockaddr_nl *nla, struct nlmsgerr *err, void *arg) in dhd_nl_error_handler() argument
40 int *ret = arg; in dhd_nl_error_handler()
45 static int dhd_nl_finish_handler(struct nl_msg *msg, void *arg) in dhd_nl_finish_handler() argument
47 int *ret = arg; in dhd_nl_finish_handler()
52 static int dhd_nl_ack_handler(struct nl_msg *msg, void *arg) in dhd_nl_ack_handler() argument
54 int *ret = arg; in dhd_nl_ack_handler()
59 static int dhd_nl_valid_handler(struct nl_msg *msg, void *arg) in dhd_nl_valid_handler() argument
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| /hardware/intel/img/hwcomposer/merrifield/ips/common/ |
| D | WsbmWrapper.c | 32 struct psb_validate_arg arg; member
35 static inline uint32_t align_to(uint32_t arg, uint32_t align) in align_to() argument
37 return ((arg + (align - 1)) & (~(align - 1))); in align_to()
83 memset(&vNode->arg.d.req, 0, sizeof(vNode->arg.d.req)); in pvrClear()
109 union drm_psb_extension_arg arg; in psbWsbmInitialize() local
130 strncpy(arg.extension, drmExt, sizeof(drmExt)); in psbWsbmInitialize()
132 ret = drmCommandWriteRead(drmFD, 6/*DRM_PSB_EXTENSION*/, &arg, sizeof(arg)); in psbWsbmInitialize()
133 if(ret || !arg.rep.exists) { in psbWsbmInitialize()
138 VTRACE("ioctl offset %#x", arg.rep.driver_ioctl_offset); in psbWsbmInitialize()
140 mainPool = wsbmTTMPoolInit(drmFD, arg.rep.driver_ioctl_offset); in psbWsbmInitialize()
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| /hardware/intel/img/psb_video/src/ |
| D | psb_buffer_dm.c | 66 struct drm_lnc_video_getparam_arg arg; in psb_buffer_info_ci() local
72 arg.key = LNC_VIDEO_GETPARAM_CI_INFO; in psb_buffer_info_ci()
73 arg.value = (uint64_t)((unsigned long) & camera_info[0]); in psb_buffer_info_ci()
75 &arg, sizeof(arg)); in psb_buffer_info_ci()
225 struct drm_lnc_video_getparam_arg arg; in psb_buffer_info_rar() local
231 arg.key = LNC_VIDEO_GETPARAM_IMR_INFO; in psb_buffer_info_rar()
232 arg.value = (uint64_t)((unsigned long) & rar_info[0]); in psb_buffer_info_rar()
234 &arg, sizeof(arg)); in psb_buffer_info_rar()
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| /hardware/qcom/wlan/cld80211-lib/ |
| D | cld80211_lib.c | 116 static int response_handler(struct nl_msg *msg, void *arg) in response_handler() argument
119 UNUSED(arg); in response_handler()
127 static int ack_handler(struct nl_msg *msg, void *arg) in ack_handler() argument
129 int *err = (int *)arg; in ack_handler()
136 static int finish_handler(struct nl_msg *msg, void *arg) in finish_handler() argument
138 int *ret = (int *)arg; in finish_handler()
146 void *arg) in error_handler() argument
148 int *ret = (int *)arg; in error_handler()
157 static int no_seq_check(struct nl_msg *msg, void *arg) in no_seq_check() argument
160 UNUSED(arg); in no_seq_check()
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