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Searched refs:out_width (Results 1 – 6 of 6) sorted by relevance

/hardware/intel/img/psb_video/src/
Dvsp_compose.c60 int out_width = 0, out_height = 0, out_stride = 0; in vsp_compose_process_pipeline_param() local
103 out_width = ALIGN_TO_16(output_surface->width); in vsp_compose_process_pipeline_param()
143 cell_compose_param->Video_OUT_xsize = out_width; in vsp_compose_process_pipeline_param()
177 cell_compose_param->scaled_width = out_width; in vsp_compose_process_pipeline_param()
179 cell_compose_param->scalefactor_dx = (unsigned int)(1024 / (((float)out_width) / yuv_width) + 0.5); in vsp_compose_process_pipeline_param()
182 (((out_width + 15) >> 4) * ((out_height + 15) >> 4)); in vsp_compose_process_pipeline_param()
/hardware/qcom/display/msm8909/gralloc/
Dgr_device_impl.h90 uint32_t *out_width, uint32_t *out_height);
/hardware/qcom/display/msm8909w_3100/libgralloc1/
Dgr_device_impl.h90 uint32_t *out_width, uint32_t *out_height);
/hardware/qcom/display/msm8996/libgralloc1/
Dgr_device_impl.h90 uint32_t *out_width, uint32_t *out_height);
/hardware/qcom/display/msm8998/libgralloc1/
Dgr_device_impl.h90 uint32_t *out_width, uint32_t *out_height);
/hardware/interfaces/neuralnetworks/1.0/
Dtypes.hal174 [batches, out_height, out_width, depth].
284 * [batches, out_height, out_width, depth_out]. For output tensor of
375 * [batches, out_height, out_width, depth_out]. For output tensor of
600 * [batches, out_height, out_width, depth].
666 * [batches, out_height, out_width, depth].
1020 * [batches, out_height, out_width, depth].