| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/ |
| D | VsyncControl.cpp | 62 return drm->writeReadIoctl(DRM_PSB_VSYNC_SET, &arg, sizeof(arg)); in control()
78 bool ret = drm->writeReadIoctl(DRM_PSB_VSYNC_SET, &arg, sizeof(arg)); in wait()
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| D | OverlayPlaneBase.cpp | 108 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| /hardware/intel/img/hwcomposer/merrifield/ips/anniedale/ |
| D | AnnCursorPlane.cpp | 184 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
207 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| D | AnnRGBPlane.cpp | 219 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
246 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| D | AnnOverlayPlane.cpp | 824 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in flush()
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/anniedale/ |
| D | AnnCursorPlane.cpp | 205 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
228 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| D | AnnRGBPlane.cpp | 277 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
304 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| D | AnnOverlayPlane.cpp | 898 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in flush()
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| /hardware/intel/img/hwcomposer/merrifield/ips/tangier/ |
| D | TngCursorPlane.cpp | 207 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
230 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| D | TngSpritePlane.cpp | 144 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
180 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
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| D | TngPrimaryPlane.cpp | 96 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in enablePlane()
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| D | TngOverlayPlane.cpp | 208 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in flush()
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| D | TngGrallocBufferMapper.cpp | 78 ret = drm->writeReadIoctl(DRM_PSB_GTT_MAP, &arg, sizeof(arg)); in gttMap()
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| /hardware/intel/img/hwcomposer/merrifield/common/base/ |
| D | Drm.h | 48 bool writeReadIoctl(unsigned long cmd, void *data,
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/common/base/ |
| D | Drm.h | 52 bool writeReadIoctl(unsigned long cmd, void *data,
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| D | Drm.cpp | 340 bool Drm::writeReadIoctl(unsigned long cmd, void *data, in writeReadIoctl() function in android::intel::Drm
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/tangier/ |
| D | TngGrallocBufferMapper.cpp | 78 ret = drm->writeReadIoctl(DRM_PSB_GTT_MAP, &arg, sizeof(arg)); in gttMap()
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| /hardware/intel/img/hwcomposer/merrifield/ips/common/ |
| D | OverlayPlaneBase.cpp | 112 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg)); in isDisabled()
|