| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/ |
| D | vector2.s | 224 r0=r1 +|+ r2, r7=r1 -|- r2(ASR);
225 r3=r4 +|+ r5, r6=r4 -|- r5(ASR);
226 r6=r7 +|+ r0, r5=r7 -|- r0(ASR);
227 r1=r2 +|+ r3, r4=r2 -|- r3(ASR);
228 r4=r3 +|+ r5, r3=r3 -|- r5(ASR);
229 r6=r3 +|+ r7, r2=r3 -|- r7(ASR);
240 r0=r1 +|+ r2, r7=r1 -|- r2(S,ASR);
241 r3=r4 +|+ r5, r6=r4 -|- r5(S,ASR);
242 r6=r7 +|+ r0, r5=r7 -|- r0(S,ASR);
243 r1=r2 +|+ r3, r4=r2 -|- r3(S,ASR);
[all …]
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| D | vector2.d | 17 24: 09 c6 01 ce R7 = VIT_MAX \(R1, R0\) \(ASR\);
19 2c: 09 c6 2c c6 R3 = VIT_MAX \(R4, R5\) \(ASR\);
21 34: 09 c6 1a c2 R1 = VIT_MAX \(R2, R3\) \(ASR\);
23 3c: 09 c6 08 ce R7 = VIT_MAX \(R0, R1\) \(ASR\);
25 44: 09 c6 3e ca R5 = VIT_MAX \(R6, R7\) \(ASR\);
27 4c: 09 c6 01 46 R3.L = VIT_MAX \(R1\) \(ASR\);
29 54: 09 c6 03 44 R2.L = VIT_MAX \(R3\) \(ASR\);
31 5c: 09 c6 07 4c R6.L = VIT_MAX \(R7\) \(ASR\);
33 64: 09 c6 04 46 R3.L = VIT_MAX \(R4\) \(ASR\);
35 6c: 09 c6 00 4e R7.L = VIT_MAX \(R0\) \(ASR\);
[all …]
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| D | bit2.s | 82 BITMUX(R0, R1, A0)(ASR);
83 BITMUX(R0, R2, A0)(ASR);
84 BITMUX(R1, R3, A0)(ASR);
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| D | bit.d | 34 2a: 08 c6 08 00 BITMUX \(R1, R0, A0\) \(ASR\);
35 2e: 08 c6 13 00 BITMUX \(R2, R3, A0\) \(ASR\);
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| D | bit2.d | 62 9c: 08 c6 01 00 BITMUX \(R0, R1, A0\) \(ASR\);
63 a0: 08 c6 02 00 BITMUX \(R0, R2, A0\) \(ASR\);
64 a4: 08 c6 0b 00 BITMUX \(R1, R3, A0\) \(ASR\);
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| D | bit.s | 44 BITMUX(R1, R0, A0) (ASR);
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| D | vector.d | 12 8: 09 c6 30 c0 R0 = VIT_MAX \(R0, R6\) \(ASR\);
14 10: 09 c6 02 44 R2.L = VIT_MAX \(R2\) \(ASR\);
29 3c: 01 c4 63 bf R5 = R4 \+\|\+ R3, R7 = R4 -\|- R3 \(SCO, ASR\);
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| D | parallel3.d | 12 10: 09 ce 30 c0 R0 = VIT_MAX \(R0, R6\) \(ASR\) \|\| \[P0--\] = P0 \|\| NOP;
16 20: 09 ce 02 44 R2.L = VIT_MAX \(R2\) \(ASR\) \|\| \[P0 \+ 0x8\] = P0 \|\| NOP;
38 78: 01 cc 63 bf R5 = R4 \+\|\+ R3, R7 = R4 -\|- R3 \(SCO, ASR\) \|\| \[P2\+\+\] = P0 \|\| NOP;
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| D | expected_errors.s | 118 BITMUX (R4, R4, A0) (ASR);
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| D | vector.s | 32 r5 = r4 +|+ r3, R7 = r4 -|- r3 (Sco, ASR);
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| D | parallel3.s | 21 r5 = r4 +|+ r3, R7 = r4 -|- r3 (Sco, ASR)|| [p2++] = P0;
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| D | parallel.d | 20 30: 08 ce 08 00 BITMUX \(R1, R0, A0\) \(ASR\) \|\| I1 -= 0x4 \|\| NOP;
22 38: 08 ce 13 00 BITMUX \(R2, R3, A0\) \(ASR\) \|\| I0 \+= 0x2 \|\| NOP;
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| D | parallel.s | 10 BITMUX(R1, R0, A0) (ASR) || I1 -= 4;
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| D | addthumb2err.s | 11 add sp, sp, r0, ASR #3
16 adds sp, sp, r0, ASR #3
21 sub sp, sp, r0, ASR #3
26 subs sp, sp, r0, ASR #3
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| D | archv6.s | 17 pkhtb r2, r5, r8, ASR #3
18 pkhtbal r2, r5, r8, ASR #3
19 pkhtbeq r2, r5, r8, ASR #3
121 ssat r1, #1, r2, ASR #2
194 usat r1, #15, r2, ASR #4
199 usatle r1, #15, r2, ASR #4
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| D | addthumb2err.l | 4 [^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR#3'
14 [^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR#3'
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| D | thumb2_bad_reg.s | 60 @ ASR (immediate)
65 @ ASR (register)
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/metag/ |
| D | metafpu21.s | 1256 F ASR FX.0,D0Re0,D0.7
1259 F ASR FX.2,D0Re0,D0.7
1262 F ASR FX.4,D0Re0,D0.7
1265 F ASR FX.7,D0Re0,D0.7
1268 F ASR FX.15,D0Re0,D0.7
1271 F ASR FX.1,D1Re0,D1.7
1274 F ASR FX.3,D1Re0,D1.7
1277 F ASR FX.5,D1Re0,D1.7
1280 F ASR FX.10,D1Re0,D1.7
1283 F ASR FX.0,D0Re0,#0x10
[all …]
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| D | metacore21.s | 1757 ASR D0.7,D0Re0,D0.7 define
1760 ASR D1.7,D1Re0,D1.7 define
1763 ASR D0Re0,D0.7,#0x1f
1766 ASR D1Re0,D1Re0,#0x10
1769 ASR D1.7,D1.7,#0xf define
1772 ASR TXENABLE,D0Re0,D0Re0
1775 ASR TXSTAT,D0Re0,D0.7
1782 ASR PCX,D0Re0,D0Re0
1785 ASR PCX,D0.7,D0Re0
1787 ASR TTMARK,D0Re0,D0Re0
[all …]
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| D | metacore12.s | 2902 ASR D0.7,D0Re0,D0Re0 define
2905 ASR D1.7,D1Re0,D1Re0 define
2908 ASR D0Re0,D0.7,#0x10
2911 ASR D1Re0,D1Re0,#0xf
2914 ASR D1.7,D1Re0,#0x1f define
2917 ASR TXENABLE,D0Re0,D0Re0
2924 ASR PC,D0.7,D0.7
2925 ASR A0FrP,D0Re0,D0Re0
2929 ASR TXMASKI,D0Re0,D0Re0
2932 ASR A1.7,D0Re0,D0Re0
[all …]
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| D | metacore21.d | 1765 .*: 50380ec0 ASR D0\.7,D0Re0,D0\.7
1768 .*: 51380ec0 ASR D1\.7,D1Re0,D1\.7
1771 .*: 5201fec0 ASR D0Re0,D0\.7,#0x1f
1774 .*: 530020c0 ASR D1Re0,D1Re0,#0x10
1777 .*: 5339dec0 ASR D1\.7,D1\.7,#0xf
1780 .*: 540000e0 ASR TXENABLE,D0Re0,D0Re0
1783 .*: 54000eee ASR TXSTAT,D0Re0,D0\.7
1790 .*: 540800ea ASR PCX,D0Re0,D0Re0
1793 .*: 5409c0ea ASR PCX,D0\.7,D0Re0
1795 .*: 541000f0 ASR TTMARK,D0Re0,D0Re0
[all …]
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| D | metafpu21.d | 1264 .*: 54000ef2 F ASR FX\.0,D0Re0,D0\.7
1267 .*: 54100ef2 F ASR FX\.2,D0Re0,D0\.7
1270 .*: 54200ef2 F ASR FX\.4,D0Re0,D0\.7
1273 .*: 54380ef2 F ASR FX\.7,D0Re0,D0\.7
1276 .*: 54780ef2 F ASR FX\.15,D0Re0,D0\.7
1279 .*: 55080ef2 F ASR FX\.1,D1Re0,D1\.7
1282 .*: 55180ef2 F ASR FX\.3,D1Re0,D1\.7
1285 .*: 55280ef2 F ASR FX\.5,D1Re0,D1\.7
1288 .*: 55500ef2 F ASR FX\.10,D1Re0,D1\.7
1291 .*: 560020f2 F ASR FX\.0,D0Re0,#0x10
[all …]
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| D | addsub.s | 160 .irp shift, LSL, LSR, ASR
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| /toolchain/binutils/binutils-2.27/gas/config/ |
| D | bfin-lex.l | 226 [aA][sS][rR] return ASR;
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| D | bfin-parse.y | 545 %token ASL ASR
3756 | LPAREN ASR RPAREN
3789 | ASR
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