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Searched refs:D33 (Results 1 – 6 of 6) sorted by relevance

/toolchain/binutils/binutils-2.27/opcodes/
Dmicromips-opc.c263 #define D33 ASE_DSPR2 macro
1271 {"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_1|RD_2, 0, 0, D33, 0 },
1272 {"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1273 {"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1274 {"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1275 {"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1276 {"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1277 {"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1278 {"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
1279 {"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
[all …]
Dmips-opc.c376 #define D33 ASE_DSPR2 macro
2367 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_1|RD_2, 0, 0, D33, 0 },
2368 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
2369 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 …
2370 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
2371 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0…
2372 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 },
2373 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 },
2374 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, MOD_1|RD_2, 0, 0, D33, 0 },
2375 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
[all …]
DChangeLog-2013953 * micromips-opc.c (D32, D33, MC): Update definitions.
958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
DChangeLog-201061 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
DChangeLog-2012543 (D32, D33): Likewise.
DChangeLog-20071750 * mips-opc.c (D33): New shortcut for DSP R2 instructions.