/toolchain/binutils/binutils-2.27/opcodes/ |
D | mips16-opc.c | 176 #define I1 INSN_ISA1 macro 185 {"nop", "", 0x6500, 0xffff, 0, RD_16, I1, 0, 0 }, /* move $0,$Z */ 186 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, 187 {"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, 188 {"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, 189 {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, 190 {"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, 191 {"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, 192 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, 193 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, [all …]
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D | micromips-opc.c | 254 #define I1 INSN_ISA1 macro 288 {"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, 0 }, 289 {"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 }, 290 {"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 }, 291 {"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 }, 292 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 293 {"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 294 {"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 295 {"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 296 {"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 }, [all …]
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D | mips-opc.c | 272 #define I1 INSN_ISA1 macro 422 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 423 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 424 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ 425 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ 426 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ 427 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, 428 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, 429 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */ 431 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */ [all …]
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D | i386-dis.c | 293 #define I1 { OP_I, const_1_mode } macro 3466 { "rolA", { Eb, I1 }, 0 }, 3467 { "rorA", { Eb, I1 }, 0 }, 3468 { "rclA", { Eb, I1 }, 0 }, 3469 { "rcrA", { Eb, I1 }, 0 }, 3470 { "shlA", { Eb, I1 }, 0 }, 3471 { "shrA", { Eb, I1 }, 0 }, 3473 { "sarA", { Eb, I1 }, 0 }, 3477 { "rolQ", { Ev, I1 }, 0 }, 3478 { "rorQ", { Ev, I1 }, 0 }, [all …]
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D | ChangeLog-2004 | 115 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define. 124 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/ |
D | parallel.d | 10 8: 0a ce 37 c0 R0 = DEPOSIT \(R7, R6\) \(X\) \|\| I1 \+= 0x4 \|\| NOP; 20 30: 08 ce 08 00 BITMUX \(R1, R0, A0\) \(ASR\) \|\| I1 -= 0x4 \|\| NOP; 34 68: 10 cc 3f 40 A0 = ABS A1 \|\| P3 = \[FP -0x3c\] \|\| R1 = \[I1 \+\+ M0\]; 36 70: 30 cc 3f 00 A1 = ABS A0 \|\| P4 = \[FP -0x4\] \|\| R2 = \[I1\+\+\]; 42 88: 07 cc 10 80 R0 = ABS R2 \|\| B\[SP\] = R0 \|\| R1.H = W\[I1\+\+\]; 54 b8: 05 cc 3d d2 R1.L = R7 - R5 \(RND20\) \|\| R0 = B\[P4\] \(Z\) \|\| \[I1\+\+\] = R7; 64 e0: 07 ce 25 0c R6.L = EXPADJ \(R5, R4.L\) \|\| R1 = B\[P3\] \(Z\) \|\| W\[I1--\] = R3.H; 70 f8: 07 cc 2a 0c R6 = MAX \(R5, R2\) \|\| R2 = B\[P0\] \(X\) \|\| W\[I1--\] = R0.L; 74 108: 07 cc 13 4a R5 = MIN \(R2, R3\) \|\| B\[P2\] = R2 \|\| R0 = \[I1\+\+\]; 76 110: 07 cc 38 48 R4 = MIN \(R7, R0\) \|\| B\[P3\] = R2 \|\| R1 = \[I1\+\+\]; [all …]
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D | parallel.s | 3 r0 = DEPOSIT (r7, R6) (X) || I1 += 4; 10 BITMUX(R1, R0, A0) (ASR) || I1 -= 4; 20 A0 = ABS A1 || P3 = [FP-60] || R1 = [I1++M0]; 24 r0 = abs r2 || B[sp] = r0 || R1.H = W[I1++]; 32 r1.L = r7 - R5 (rND20) || r0 = b [p4] (z) || [I1++] = R7; 40 r6.L = EXPADJ (r5, r4.l) || r1 = b [p3] (z) || W[I1--]=r3.h; 78 A0 += r4.h * r1.L || r5 = b [p2] (z) || [I1++M1] = R7; 145 R4.L = A0.x || R6 = [FP + 60] || R4.H = W[I1++] ; 146 R4.L = A0.x || R4.H = W[I1++] || W[I0] = R4.H ; 147 R4.L = A0.x || W[I1++] = R4.L || R4.H = W[I0--] ; [all …]
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D | move2.s | 75 R1 = I1; 93 P1 = I1; 112 A0.W = I1; 133 I1 = P0; define 137 I1 = A0.W; define 171 I0 = I1; 172 I1 = M0; define 176 M0 = I1; 181 B0 = I1; 186 L0 = I1;
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D | move2.d | 61 6a: 89 30 R1 = I1; 77 8a: 89 32 P1 = I1; 93 aa: 89 38 A0.W = I1; 109 ca: 48 34 I1 = P0; 113 d2: 09 35 I1 = A0.W; 140 108: 81 34 I0 = I1; 141 10a: 8c 34 I1 = M0; 144 110: a1 34 M0 = I1; 148 118: 81 36 B0 = I1; 152 120: a1 36 L0 = I1;
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D | parallel4.d | 14 18: 12 cc 00 c0 DISALGNEXCPT \|\| \[I1\] = R0 \|\| NOP; 16 20: 17 cc 02 0a R5 = BYTEOP3P \(R1:0, R3:2\) \(LO\) \|\| \[I1\+\+\] = R0 \|\| NOP; 18 28: 37 cc 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(HI\) \|\| \[I1--\] = R0 \|\| NOP;
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D | stack2.s | 18 [--SP ] = I1; 75 I1= [ SP ++ ] ;
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D | store.d | 28 2c: 8f 9f \[I1 \+\+ M0\] = R7; 39 3a: 2f 9e W\[I1\+\+\] = R7.L;
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D | load.d | 60 98: 09 9c R1 = \[I1\+\+\]; 84 c4: 49 9c R1.H = W\[I1\+\+\]; 92 d0: ad 9c R5.L = W\[I1--\];
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D | stack2.d | 13 a: 51 01 \[--SP\] = I1; 49 52: 11 01 I1 = \[SP\+\+\];
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D | parallel5.s | 4 R0 = W[P1++] (X) || R1.L = W[I1++];
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D | load.s | 70 r1 = [I1++]; 100 R1.H = W [I1 ++];
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D | parallel2.d | 38 78: 09 cc 20 80 A1.L = R4.L \|\| R0 = \[I1 \+\+ M3\] \|\| NOP; 40 80: 29 cc 30 00 A0.H = R6.H \|\| R0 = \[I1 \+\+ M2\] \|\| NOP; 42 88: 29 cc 28 80 A1.H = R5.H \|\| R0 = \[I1 \+\+ M1\] \|\| NOP; 44 90: 83 c9 00 38 R0.L = A0 \(IU\) \|\| R4 = \[I1 \+\+ M0\] \|\| NOP;
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D | pseudo.s | 24 DBG I1;
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D | parallel3.d | 126 …1d8: 2d c9 3e e8 R1 = \(A1 \+= R7.H \* R6.H\), R0 = \(A0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[I1\] … 128 …1e0: 0d c8 37 e1 R5 = \(A1 \+= R6.H \* R7.H\), R4 = \(A0 = R6.L \* R7.L\) \|\| \[I1\+\+\] = R3 \|… 130 …1e8: 0d c8 9d f1 R7 = \(A1 \+= R3.H \* R5.H\), R6 = \(A0 -= R3.L \* R5.L\) \|\| \[I1--\] = R3 \|\…
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D | pseudo.d | 24 22: 11 f8 DBG I1;
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D | arithmetic.d | 43 58: 69 9f I1 \+= 0x4;.* 71 8e: 75 9e I1 -= M1;
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D | video2.d | 135 [ 0-9a-f]+: 12 cc 02 00 SAA \(R1:0, R3:2\) \|\| R0 = \[I0\+\+\] \|\| R2 = \[I1\+\+\]; 137 [ 0-9a-f]+: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\];
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D | vector2.d | 452 6f0: 12 cc 02 00 SAA \(R1:0, R3:2\) \|\| R0 = \[I0\+\+\] \|\| R2 = \[I1\+\+\]; 454 6f8: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\]; 456 700: 03 c8 00 18 MNOP \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\]; 464 …720: 01 c8 02 48 A1 \+= R0.L \* R2.H, A0 \+= R0.L \* R2.L \|\| R2.L = W\[I2\+\+\] \|\| R0 = \[I1-…
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/toolchain/binutils/binutils-2.27/cpu/ |
D | frv.opc | 283 /* I1 */ UNIT_I1, 287 /* IALL */ UNIT_I01, /* only I0 and I1 units */ 300 /* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ 318 /* I1 */ UNIT_I1, 322 /* IALL */ UNIT_I01, /* only I0 and I1 units */ 335 /* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ 350 /* I1 */ UNIT_I1, 354 /* IALL */ UNIT_I01, /* only I0 and I1 units */ 366 /* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ 368 /* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ [all …]
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/toolchain/binutils/binutils-2.27/gas/doc/ |
D | c-bfin.texi | 215 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
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