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/toolchain/binutils/binutils-2.27/opcodes/
Dmips16-opc.c177 #define I3 INSN_ISA3 macro
231 {"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
232 {"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
233 {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
234 {"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
235 {"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
236 {"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
237 {"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
238 {"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
239 {"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
[all …]
Dmicromips-opc.c255 #define I3 INSN_ISA3 macro
303 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */
562 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 },
563 {"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
564 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 },
565 {"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 },
566 {"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 },
567 {"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
568 {"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
569 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
[all …]
Dmips-opc.c274 #define I3 INSN_ISA3 macro
430 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */
984 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 },
985 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
986 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 },
989 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 },
990 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
991 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
992 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
1000 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/
Dparallel.d14 18: 0a ce 10 04 R2 = EXTRACT \(R0, R2.L\) \(Z\) \|\| I3 \+= M1 \|\| NOP;
16 20: 0a ce 23 4e R7 = EXTRACT \(R3, R4.L\) \(X\) \|\| I3 \+= M1 \(BREV\) \|\| NOP;
46 98: 22 cc 09 aa R5.H = R1.H \+ R1.L \(S\) \|\| B\[P0\] = R0 \|\| R3.L = W\[I3\];
48 a0: 02 cc 35 0c R6.L = R6.L \+ R5.L \(NS\) \|\| B\[P1\] = R0 \|\| R4.L = W\[I3\+\+\];
58 c8: 25 cc 3e 0e R7.H = R7 \+ R6 \(RND12\) \|\| R1 = B\[P0\] \(X\) \|\| \[I3 \+\+ M1\] = R6;
60 d0: 05 cc 1a 4a R5.L = R3 - R2 \(RND12\) \|\| R1 = B\[P1\] \(Z\) \|\| W\[I3\] = R5.H;
154 248: 04 c8 48 58 R1.H = \(A1 = R1.L \* R0.H\) \|\| R2.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R7;
156 …250: 34 c9 83 98 R2.H = \(A1 = R0.H \* R3.L\) \(M, ISS2\) \|\| R3.L = W\[I1\+\+\] \|\| \[I3 \+\+ …
158 258: 05 c8 bf 59 R6.H = \(A1 \+= R7.L \* R7.H\) \|\| R4.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R5;
160 …260: 25 c8 d3 19 R7.H = \(A1 \+= R2.L \* R3.L\) \(S2RND\) \|\| R5.L = W\[I1\+\+\] \|\| \[I3 \+\+ …
[all …]
Dparallel4.d26 48: 15 cc 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\) \|\| \[I3\] = R0 \|\| NOP;
28 50: 15 cc 82 21 \(R6, R0\) = BYTEOP16P \(R1:0, R3:2\) \(R\) \|\| \[I3\+\+\] = R0 \|\| NOP;
30 58: 14 cc 02 4e R7 = BYTEOP1P \(R1:0, R3:2\) \(T\) \|\| \[I3--\] = R0 \|\| NOP;
Dstore.d27 2a: 9c 9e \[I3--\] = R4;
31 2e: 5c 9f W\[I3\] = R4.H;
Dmove2.s77 R3 = I3;
95 P3 = I3;
114 A1.W = I3;
135 I3 = FP; define
139 I3 = A1.W; define
174 I3 = L0; define
Dparallel2.d54 b8: 47 c8 00 38 R0.H = A1, R0.L = A0 \(T\) \|\| R5 = \[I3 \+\+ M0\] \|\| NOP;
56 c0: 87 c8 00 38 R0.H = A1, R0.L = A0 \(FU\) \|\| R5 = \[I3 \+\+ M1\] \|\| NOP;
58 c8: 07 c9 00 38 R0.H = A1, R0.L = A0 \(IS\) \|\| R5 = \[I3 \+\+ M2\] \|\| NOP;
60 d0: 07 c8 00 38 R0.H = A1, R0.L = A0 \|\| R5 = \[I3 \+\+ M3\] \|\| NOP;
Dmove2.d63 6e: 9b 30 R3 = I3;
79 8e: 9b 32 P3 = I3;
95 ae: 9b 38 A1.W = I3;
111 ce: 5f 34 I3 = FP;
115 d6: 1b 35 I3 = A1.W;
143 10e: dc 34 I3 = L0;
Dload.d62 9c: 9c 9d R4 = \[I3 \+\+ M0\];
90 cc: 3f 9d R7.L = W\[I3\];
Dparallel.s7 r7 = ExtracT (r3, r4.L) (X) || I3 += M1 (breV);
27 r5.H = R1.H + R1.L (S) || b [p0] = r0 || R3.l = W[I3];
35 r7.H = r7 + r6 (RND12) || r1 = b [p0] (x)|| [I3++m1]=r6;
135 r3.l = signBits A0 || r2 = w [p2++] (x) || [I3] = R0;
Dpseudo.s26 DBG I3;
Darithmetic.s46 I3 += 2;
86 I3 -= M0;
Dparallel3.d138 208: 2f c8 81 28 R3 = A1, R2 = \(A0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[I3\] = R7 \|\| NOP;
140 …210: 0d c9 1a e0 R1 = \(A1 \+= R3.H \* R2.H\), R0 = \(A0 = R3.L \* R2.L\) \(IS\) \|\| \[I3\+\+\] …
142 218: 0f cc 08 c0 R0 = -R1 \(V\) \|\| \[I3--\] = R6 \|\| NOP;
Dpseudo.d26 26: 13 f8 DBG I3;
Darithmetic.d41 54: 63 9f I3 \+= 0x2;.*
70 8c: 73 9e I3 -= M0;
Dvector2.s655 A1=R2.L*R1.L, A0=R2.H*R1.H || R2.H=W[I2++] || [I3++]=R3 ;
Dvector2.d462 …718: 00 c8 11 06 A1 = R2.L \* R1.L, A0 = R2.H \* R1.H \|\| R2.H = W\[I2\+\+\] \|\| \[I3\+\+\] = R…
/toolchain/binutils/binutils-2.27/cpu/
Dfrv.opc285 /* I2 */ UNIT_NIL, /* no I2 or I3 unit */
286 /* I3 */ UNIT_NIL,
320 /* I2 */ UNIT_NIL, /* no I2 or I3 unit */
321 /* I3 */ UNIT_NIL,
352 /* I2 */ UNIT_NIL, /* no I2 or I3 unit */
353 /* I3 */ UNIT_NIL,
385 /* I3 */ UNIT_I3,
Dfrv.cpu1771 I0 I1 I01 I2 I3 IALL
/toolchain/binutils/binutils-2.27/gas/doc/
Dc-bfin.texi215 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
/toolchain/benchmark/panorama_input/
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