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Searched refs:LSR (Results 1 – 16 of 16) sorted by relevance

/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Daddthumb2err.s10 add sp, sp, r0, LSR #3
15 adds sp, sp, r0, LSR #3
20 sub sp, sp, r0, LSR #3
25 subs sp, sp, r0, LSR #3
Daddthumb2err.l8 [^:]*:15: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,LSR#3'
18 [^:]*:25: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,LSR#3'
Dthumb2_bad_reg.s149 @ LSR (immediate)
154 @ LSR (register)
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/epiphany/
Dregression.s170 LSRLAB: LSR R63,R6,#0x2 ; //6>>2=1
175 LSRILAB: LSR R63,R6,R2 ; //6>>2=1
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/metag/
Dmetacore12.s2903 LSR D0.7,D0.7,D0.7 define
2906 LSR D1.7,D1.7,D1.7 define
2909 LSR D0.7,D0Re0,#0x10 define
2912 LSR D1Re0,D1.7,#0xf
2915 LSR D1.7,D1.7,#0x1f define
2921 LSR PC,D0.7,D0Re0
2923 LSR TXENABLE,D0.7,D0.7
2926 LSR PCX,D0Re0,D0.7
2927 LSR A1LbP,D0.7,D0Re0
2928 LSR A0FrP,D0.7,D0.7
[all …]
Dmetacore21.s1755 LSR D0Re0,D0Re0,D0Re0
1758 LSR D1Re0,D1Re0,D1Re0
1761 LSR D0Re0,D0Re0,#0xf
1764 LSR D0.7,D0Re0,#0x1f define
1767 LSR D1Re0,D1.7,#0x10
1774 LSR D1Re0,D0Re0,D0.7
1783 LSR PCX,D0Re0,D0.7
1786 LSR PCX,D0.7,D0.7
1788 LSR TTMARK,D0.7,D0.7
1790 LSR TXMASKI,D0.7,D0Re0
[all …]
Dmetafpu21.s1257 F LSR FX.1,D0Re0,D0Re0
1260 F LSR FX.3,D0Re0,D0Re0
1263 F LSR FX.5,D0Re0,D0Re0
1266 F LSR FX.10,D0Re0,D0Re0
1269 F LSR FX.0,D1Re0,D1Re0
1272 F LSR FX.2,D1Re0,D1Re0
1275 F LSR FX.4,D1Re0,D1Re0
1278 F LSR FX.7,D1Re0,D1Re0
1281 F LSR FX.15,D1Re0,D1Re0
1284 F LSR FX.0,D0.7,#0x10
[all …]
Dmetacore21.d1763 .*: 50000040 LSR D0Re0,D0Re0,D0Re0
1766 .*: 51000040 LSR D1Re0,D1Re0,D1Re0
1769 .*: 52001e40 LSR D0Re0,D0Re0,#0xf
1772 .*: 52383e40 LSR D0\.7,D0Re0,#0x1f
1775 .*: 5301e040 LSR D1Re0,D1\.7,#0x10
1782 .*: 54000e64 LSR D1Re0,D0Re0,D0\.7
1791 .*: 54080e6a LSR PCX,D0Re0,D0\.7
1794 .*: 5409ce6a LSR PCX,D0\.7,D0\.7
1796 .*: 5411ce70 LSR TTMARK,D0\.7,D0\.7
1798 .*: 5419c06e LSR TXMASKI,D0\.7,D0Re0
[all …]
Dmetafpu21.d1265 .*: 54080072 F LSR FX\.1,D0Re0,D0Re0
1268 .*: 54180072 F LSR FX\.3,D0Re0,D0Re0
1271 .*: 54280072 F LSR FX\.5,D0Re0,D0Re0
1274 .*: 54500072 F LSR FX\.10,D0Re0,D0Re0
1277 .*: 55000072 F LSR FX\.0,D1Re0,D1Re0
1280 .*: 55100072 F LSR FX\.2,D1Re0,D1Re0
1283 .*: 55200072 F LSR FX\.4,D1Re0,D1Re0
1286 .*: 55380072 F LSR FX\.7,D1Re0,D1Re0
1289 .*: 55780072 F LSR FX\.15,D1Re0,D1Re0
1292 .*: 5601e072 F LSR FX\.0,D0\.7,#0x10
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Daddsub.s160 .irp shift, LSL, LSR, ASR
Dillegal.s483 add x0, x1, #20, LSR
Dillegal.l511 [^:]*:483: Error: .*`add x0,x1,#20,LSR'
/toolchain/binutils/binutils-2.27/cpu/
Dmt.cpu277 LSL LSR ASR - - - - -
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
Dcris.cpu1677 "AND" "OR" "ASR" "LSR")
3772 ; LSR.m Rs,Rd [ Rd | 011111mm | Rs ]
Depiphany.cpu323 (EOR ADD LSL SUB LSR AND ASR ORR))
/toolchain/binutils/binutils-2.27/gas/
DChangeLog-00015265 Issue a warning if "ASR #0" or "LSR #0" is used.