/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/ |
D | insns16-m-unit.d | 11 [0-9a-f]+[02468ace] <[^>]*> 469f[ \t]+mpy \.M2 b2,b5,b2 15 [0-9a-f]+[02468ace] <[^>]*> ca9f[ \t]+mpy \.M2 b6,b5,b4 18 [0-9a-f]+[02468ace] <[^>]*> 46bf[ \t]+mpyh \.M2 b2,b5,b2 22 [0-9a-f]+[02468ace] <[^>]*> cabf[ \t]+mpyh \.M2 b6,b5,b4 26 [0-9a-f]+[02468ace] <[^>]*> 47df[ \t]+mpylh \.M2 b18,b23,b18 30 [0-9a-f]+[02468ace] <[^>]*> cbdf[ \t]+mpylh \.M2 b22,b23,b20 33 [0-9a-f]+[02468ace] <[^>]*> 45ff[ \t]+mpyhl \.M2 b18,b19,b18 37 [0-9a-f]+[02468ace] <[^>]*> c9ff[ \t]+mpyhl \.M2 b22,b19,b20 41 [0-9a-f]+[02468ace] <[^>]*> 469f[ \t]+smpy \.M2 b18,b21,b18 45 [0-9a-f]+[02468ace] <[^>]*> ca9f[ \t]+smpy \.M2 b22,b21,b20 [all …]
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D | predicate-bad-3.s | 16 [!b1] ddotp4 .M2 b0,b1,b3:b2 17 [!a0] ddotph2 .M2 b1:b0,b2,b5:b4 18 [!a0] ddotph2r .M2 b1:b0,b2,b5 19 [!a0] ddotpl2 .M2 b1:b0,b2,b5:b4 20 [!a0] ddotpl2r .M2 b1:b0,b2,b5
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D | insns-c674x.s | 171 avg2 .M2 b26,b29,b0 175 avgu4 .M2 b26,b29,b0 196 bitc4 .M2 b16,b26 200 bitr .M2 b16,b26 356 cmpy .M2 b8,b9,b11:b10 360 cmpyr .M2 b8,b9,b11 364 cmpyr1 .M2 b8,b9,b11 368 ddotp4 .M2 b8,b9,b11:b10 372 ddotph2 .M2 b7:b6,b9,b11:b10 376 ddotph2r .M2 b7:b6,b9,b11 [all …]
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D | insns-c674x-sploop.d | 17 [0-9a-f]+[048c] <[^>]*> 02030000[ \t]+spmask M2 20 [0-9a-f]+[048c] <[^>]*> 03ff0000[ \t]+spmask L1,L2,S1,S2,D1,D2,M1,M2 33 [0-9a-f]+[048c] <[^>]*> 02032000[ \t]+spmaskr M2 36 [0-9a-f]+[048c] <[^>]*> 03ff2000[ \t]+spmaskr L1,L2,S1,S2,D1,D2,M1,M2
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D | insns-c674x.d | 174 [0-9a-f]+[048c] <[^>]*> 007744f2[ \t]+avg2 \.M2 b26,b29,b0 178 [0-9a-f]+[048c] <[^>]*> 007744b2[ \t]+avgu4 \.M2 b26,b29,b0 199 [0-9a-f]+[048c] <[^>]*> 0d43c0f2[ \t]+bitc4 \.M2 b16,b26 203 [0-9a-f]+[048c] <[^>]*> 0d43e0f2[ \t]+bitr \.M2 b16,b26 359 [0-9a-f]+[048c] <[^>]*> 152502b2[ \t]+cmpy \.M2 b8,b9,b11:b10 363 [0-9a-f]+[048c] <[^>]*> 15a502f2[ \t]+cmpyr \.M2 b8,b9,b11 367 [0-9a-f]+[048c] <[^>]*> 15a50332[ \t]+cmpyr1 \.M2 b8,b9,b11 371 [0-9a-f]+[048c] <[^>]*> 15250632[ \t]+ddotp4 \.M2 b8,b9,b11:b10 375 [0-9a-f]+[048c] <[^>]*> 1524c5f2[ \t]+ddotph2 \.M2 b7:b6,b9,b11:b10 379 [0-9a-f]+[048c] <[^>]*> 15a4c572[ \t]+ddotph2r \.M2 b7:b6,b9,b11 [all …]
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D | insns-c674x-sploop.s | 20 spmask L1,S1,D1,M1,M2,D2,S2,L2 36 spmaskr L1,S1,D1,M1,M2,D2,S2,L2
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D | insns-bad-1.s | 193 and .M2 b1,b2,b3 215 call .M2 b1 224 b .M2 nrp 227 bitc4 .M2 b2,a1 231 bitr .M2 b2,a1 244 clr .M2 b1,b2,b3 270 cmpeqsp .M2 b1,b2,b3 352 ddotp4 .M2 a1,b1,b3:b2 356 ddotph2 .M2 a1:a0,b1,b3:b2 360 ddotph2r .M2 a1:a0,b1,b3 [all …]
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/frv/ |
D | fr450-media-issue.s | 5 mcpli fr4,#1,fr6 ; M2 -- error 16 mqaddhss.p fr0,fr2,fr2 ; M2 18 mqaddhss.p fr0,fr2,fr2 ; M2 19 mcpli fr4,#1,fr6 ; M2 -- error 20 mqaddhss.p fr0,fr2,fr2 ; M2 22 mqaddhss.p fr0,fr2,fr2 ; M2 24 mqaddhss.p fr0,fr2,fr2 ; M2 26 mqaddhss.p fr0,fr2,fr2 ; M2 33 mcpli fr4,#1,fr6 ; M2 -- error 47 mcpli fr4,#1,fr6 ; M2 -- error [all …]
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/ |
D | expected_errors.s | 13 A1 -= M2.h * R3.L, A0 -= M2.l * R3.L; 57 [ R0 ++ M2 ] = R2; 61 [ P0 ++ M2 ] = R2; 64 W [ R0 ++ M2 ] = R2.h; 68 W [ P0 ++ M2 ] = R2.h; 85 R2 = [ R0 ++ M2 ]; 89 R2 = [ P0 ++ M2 ]; 92 R2.h = W [ R0 ++ M2 ]; 96 R2.h = W [ P0 ++ M2 ];
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D | move2.s | 80 R6 = M2; 98 SP = M2; 118 A1.X = M2; 143 M2 = SP; define 147 M2 = A1.X; define 178 M2 = B1; define
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D | parallel.d | 138 208: 02 c9 03 58 A1 -= R0.L \* R3.H \(IS\) \|\| R2.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R0; 140 210: 02 c8 17 58 A1 -= R2.L \* R7.H \|\| R3.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R1; 142 218: 03 c8 f5 25 R7.L = \(A0 = R6.H \* R5.L\) \|\| R4.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R2; 144 …220: c3 c8 0a 24 R0.L = \(A0 = R1.H \* R2.L\) \(TFU\) \|\| R5.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R… 146 228: 03 c8 ac 28 R2.L = \(A0 \+= R5.L \* R4.L\) \|\| R6.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R4; 148 …230: 43 c8 fe 2e R3.L = \(A0 \+= R7.H \* R6.H\) \(T\) \|\| R7.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R… 150 238: 03 c8 1a 36 R0.L = \(A0 -= R3.H \* R2.H\) \|\| R7.L = W\[I1\+\+\] \|\| \[I2 \+\+ M2\] = R6; 152 …240: 63 c9 6c 30 R1.L = \(A0 -= R5.L \* R4.L\) \(IH\) \|\| R6.L = W\[I1\+\+\] \|\| \[I2 \+\+ M2\]… 204 310: 2c cc 00 cc R6.H = R0 \(RND\) \|\| W\[P1\] = R3 \|\| R1 = \[I1 \+\+ M2\];
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D | parallel2.d | 34 68: 0a cc 3f 4e R7.L = A1.X \|\| R0 = \[I0 \+\+ M2\] \|\| NOP; 40 80: 29 cc 30 00 A0.H = R6.H \|\| R0 = \[I1 \+\+ M2\] \|\| NOP; 50 a8: 67 c9 80 38 R2.H = A1, R2.L = A0 \(IH\) \|\| R0 = \[I2 \+\+ M2\] \|\| NOP; 58 c8: 07 c9 00 38 R0.H = A1, R0.L = A0 \(IS\) \|\| R5 = \[I3 \+\+ M2\] \|\| NOP;
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D | move2.d | 66 74: b6 30 R6 = M2; 82 94: b6 32 SP = M2; 98 b4: 96 38 A1.X = M2; 118 dc: 76 34 M2 = SP; 122 e4: 32 35 M2 = A1.X; 146 114: f1 34 M2 = B1;
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D | pseudo.s | 29 DBG M2;
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D | move.s | 7 M2 = i2; define
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D | pseudo.d | 29 2c: 16 f8 DBG M2;
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D | move.d | 11 6: b2 34 M2 = I2;
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D | load.d | 31 54: 36 e1 ff 7f M2 = 0x7fff \(X\);.*
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D | arithmetic.s | 96 i2 += M2;
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D | arithmetic.d | 78 9c: 6a 9e I2 \+= M2;
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D | parallel.s | 89 a1 -= r2.l * r7.h || r3.l = w [i0] || [I2++M2] =R1;
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/toolchain/binutils/binutils-2.27/opcodes/ |
D | ia64-opc-m.c | 26 #define M2 IA64_TYPE_M, 2 macro 208 {"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY}, 210 {"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY}, 212 {"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY}, 274 {"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY}, 276 {"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY}, 278 {"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY}, 730 {"ld16", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 0, 0), {R1, AR_CSD, MR3}, EMPTY}, 732 {"ld16.nt1", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 0), {R1, AR_CSD, MR3}, EMPTY}, 733 {"ld16.d1", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 0), {R1, AR_CSD, MR3}, PSEUDO, 0, NULL}, [all …]
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/toolchain/binutils/binutils-2.27/include/opcode/ |
D | i960.h | 52 #define M2 0x1000 macro 74 #define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ 75 #define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ 76 #define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ 78 #define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */
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/toolchain/binutils/binutils-2.27/cpu/ |
D | frv.opc | 291 /* FM2 */ UNIT_NIL, /* no F2 or M2 units */ 326 /* FM2 */ UNIT_NIL, /* no F2 or M2 units */ 358 /* FM2 */ UNIT_NIL, /* no F2 or M2 units */ 359 /* FM3 */ UNIT_NIL, /* no F3 or M2 units */
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/toolchain/binutils/binutils-2.27/gas/doc/ |
D | c-bfin.texi | 219 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
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