Home
last modified time | relevance | path

Searched refs:P2 (Results 1 – 25 of 48) sorted by relevance

12

/toolchain/binutils/binutils-2.27/opcodes/
Dia64-opc-a.c150 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
151 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
152 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
153 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
154 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
155 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
156 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
157 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
158 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
159 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
[all …]
Dtic80-opc.c556 #define P2(x) ((x) << 7) macro
768 …{"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E…
769 …{"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E…
770 …{"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, R…
771 …{"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, …
772 …{"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, R…
773 …{"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, …
774 …{"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, R…
775 …{"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, …
779 …{"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E…
[all …]
Dia64-opc-f.c89 {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY},
90 {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL},
91 {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY},
92 {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY},
93 {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY},
95 {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY},
96 {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL},
97 {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY},
98 {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY},
99 {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY},
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/
Dflow.s59 P2 = P0 << 2; define
60 P2 = P2 + FP; define
63 P2 = P2 + P1; define
65 [P2] = R0;
95 P2 = P0 << 2; define
96 P2 = P2 + FP; define
99 P1 = P2 + P0;
102 P2 = P0 << 2; define
103 P2 = P2 + FP; define
106 P2 = P2 + P0; define
[all …]
Dflow.d29 28: 72 00 CALL \(PC \+ P2\);
47 50: 42 44 P2 = P0 << 0x2;
48 52: ba 5a P2 = P2 \+ FP;
51 5a: 8a 5a P2 = P2 \+ P1;
53 5e: 10 93 \[P2\] = R0;
73 9e: 42 44 P2 = P0 << 0x2;
74 a0: ba 5a P2 = P2 \+ FP;
77 a8: 42 5a P1 = P2 \+ P0;
80 b0: 42 44 P2 = P0 << 0x2;
81 b2: ba 5a P2 = P2 \+ FP;
[all …]
Dcontrol_code2.s75 CC = P0 == P2;
82 CC = P2 == -4;
83 CC = P2 == 0;
84 CC = P2 == 3;
89 CC = P0 < P2;
96 CC = P2 < -4;
97 CC = P2 < 0;
98 CC = P2 < 3;
104 CC = P0 <= P2;
111 CC = P2 <= -4;
[all …]
Dallinsn16.d90 [^:]+: 52 00 + JUMP \(P2\);
106 [^:]+: 62 00 + CALL \(P2\);
122 [^:]+: 72 00 + CALL \(PC \+ P2\);
138 [^:]+: 82 00 + JUMP \(PC \+ P2\);
186 [^:]+: b2 00 + TESTSET \(P2\);
338 [^:]+: 4a 01 + \[--SP\] = P2;
586 [^:]+: 42 02 + PREFETCH\[P2\];
594 [^:]+: 4a 02 + FLUSHINV\[P2\];
602 [^:]+: 52 02 + FLUSH\[P2\];
610 [^:]+: 5a 02 + IFLUSH\[P2\];
[all …]
Dexpected_errors.s59 [ R0 ++ P2 ] = R2;
62 [ I0 ++ P2 ] = R2;
66 W [ R0 ++ P2 ] = R2.h;
69 W [ I0 ++ P2 ] = R2.h;
72 [ I0 ++ ] = P2;
75 W [ I0 ++ ] = P2.h;
79 W [ P0 ++ ] = P2;
83 B [ P0 ++ ] = P2;
87 R2 = [ R0 ++ P2 ];
90 R2 = [ I0 ++ P2 ];
[all …]
Dparallel2.s51 r7.l = r0.L << 0 || R5 = W [P2] (z);
52 r5 = r5 >> 31 || R7 = W [P2++] (z);
53 r0 = r0 << 12 || R5 = W [P2--] (z);
54 A0 = A0 >> 1 || R5 = W [P2+0] (z);
55 A0 = A0 << 0 || R5 = W [P2+2] (z);
56 a1 = A1 << 31 || R5 = W [P2+4] (z);
57 a1 = a1 >> 16 || R5 = W [P2+30] (z);
59 R1.H = LShift r2.h by r0.l || R5 = W [P2+24] (z);
60 r0.l = LSHIFT r0.h by r1.l || R5 = W [P2+22] (z);
61 r7.L = lshift r6.L BY r2.l || R5 = W [P2+20] (z);
[all …]
Dcontrol_code2.d52 5a: 50 08 CC = P0 == P2;
57 64: 62 0c CC = P2 == -0x4;
58 66: 42 0c CC = P2 == 0x0;
59 68: 5a 0c CC = P2 == 0x3;
62 6e: d0 08 CC = P0 < P2;
67 78: e2 0c CC = P2 < -0x4;
68 7a: c2 0c CC = P2 < 0x0;
69 7c: da 0c CC = P2 < 0x3;
72 82: 50 09 CC = P0 <= P2;
77 8c: 62 0d CC = P2 <= -0x4;
[all …]
Dcache2.s12 PREFETCH [ P2 ] ;
22 PREFETCH [ P2++ ] ;
32 FLUSH [ P2 ] ;
41 FLUSH [ P2++ ] ;
51 FLUSHINV [ P2 ] ;
61 FLUSHINV [ P2++ ] ;
71 IFLUSH [ P2 ] ;
81 IFLUSH [ P2++ ] ;
Dloop_temps.s79 P2 = P1 << 2; define
80 SP -= P2;
150 P2 = P1 << 2; define
151 SP -= P2;
178 P2 = R0; define
179 R0 = W [P2] (Z);
192 P2 = R0; define
193 R0 = W [P2] (Z);
208 P2 = [FP+-16]; define
209 I2 = P2;
[all …]
Dshift2.s12 P2 = (P2+P0)<<1; define
13 P1 = (P1+P2)<<1;
20 P2 = (P2+P0)<<2; define
21 P1 = (P1+P2)<<2;
45 P0 = P0 + (P2 << 1);
46 P0 = P1 + (P2 << 1);
47 P0 = P2 + (P3 << 1);
50 P1 = P0 + (P2 << 1);
51 P1 = P1 + (P2 << 1);
52 P1 = P2 + (P3 << 1);
[all …]
Dcache2.d9 4: 42 02 PREFETCH\[P2\];
17 14: 62 02 PREFETCH\[P2\+\+\];
25 24: 52 02 FLUSH\[P2\];
33 34: 72 02 FLUSH\[P2\+\+\];
41 44: 4a 02 FLUSHINV\[P2\];
49 54: 6a 02 FLUSHINV\[P2\+\+\];
57 64: 5a 02 IFLUSH\[P2\];
65 74: 7a 02 IFLUSH\[P2\+\+\];
Dparallel2.d96 160: 80 ce 00 8e R7.L = R0.L << 0x0 \|\| R5 = W\[P2\] \(Z\) \|\| NOP;
98 168: 82 ce 0d 8b R5 = R5 >> 0x1f \|\| R7 = W\[P2\+\+\] \(Z\) \|\| NOP;
100 170: 82 ce 60 80 R0 = R0 << 0xc \|\| R5 = W\[P2--\] \(Z\) \|\| NOP;
102 178: 83 ce f8 41 A0 = A0 >> 0x1 \|\| R5 = W\[P2 \+ 0x0\] \(Z\) \|\| NOP;
104 180: 83 ce 00 00 A0 = A0 << 0x0 \|\| R5 = W\[P2 \+ 0x2\] \(Z\) \|\| NOP;
106 188: 83 ce f8 10 A1 = A1 << 0x1f \|\| R5 = W\[P2 \+ 0x4\] \(Z\) \|\| NOP;
108 190: 83 ce 80 51 A1 = A1 >> 0x10 \|\| R5 = W\[P2 \+ 0x1e\] \(Z\) \|\| NOP;
110 198: 00 ce 02 b2 R1.H = LSHIFT R2.H BY R0.L \|\| R5 = W\[P2 \+ 0x18\] \(Z\) \|\| NOP;
112 1a0: 00 ce 08 90 R0.L = LSHIFT R0.H BY R1.L \|\| R5 = W\[P2 \+ 0x16\] \(Z\) \|\| NOP;
114 1a8: 00 ce 16 8e R7.L = LSHIFT R6.L BY R2.L \|\| R5 = W\[P2 \+ 0x14\] \(Z\) \|\| NOP;
[all …]
Dshift2.d10 4: 82 45 P2 = \(P2 \+ P0\) << 0x1;
11 6: 91 45 P1 = \(P1 \+ P2\) << 0x1;
14 c: c2 45 P2 = \(P2 \+ P0\) << 0x2;
15 e: d1 45 P1 = \(P1 \+ P2\) << 0x2;
26 24: 10 5c P0 = P0 \+ \(P2 << 0x1\);
27 26: 11 5c P0 = P1 \+ \(P2 << 0x1\);
28 28: 1a 5c P0 = P2 \+ \(P3 << 0x1\);
31 2e: 50 5c P1 = P0 \+ \(P2 << 0x1\);
32 30: 51 5c P1 = P1 \+ \(P2 << 0x1\);
33 32: 5a 5c P1 = P2 \+ \(P3 << 0x1\);
[all …]
Dstore.d10 6: d6 bf \[P2 \+ 0x3c\] = SP;
12 c: 3a bc \[FP \+ 0x0\] = P2;
17 12: 10 93 \[P2\] = R0;
42 40: 13 97 W\[P2\] = R3;
46 48: 56 e6 ff 7f W\[P2 \+ 0xfffe\] = R6;
48 50: 56 8b W\[SP \+\+ P2\] = R5.L;
54 58: 97 e6 19 00 B\[P2 \+ 0x19\] = R7;
Dmove2.s21 P2 = P2; define
44 P1 = P2;
45 P2 = P1; define
94 P2 = I2; define
103 P2 = B2; define
193 P2 = USP; define
253 LC1 = P2;
323 IF CC R2 = P2;
328 IF CC P0 = P2;
336 IF CC P2 = R6;
[all …]
Dflow2.s15 JUMP (P2);
25 JUMP (PC+P2);
101 CALL(P2);
110 CALL(PC+P2);
Dmove2.d18 14: 52 32 P2 = P2;
37 3a: 4a 32 P1 = P2;
38 3c: 51 32 P2 = P1;
78 8c: 92 32 P2 = I2;
86 9c: d2 32 P2 = B2;
157 12a: d0 33 P2 = USP;
209 192: 5a 3c LC1 = P2;
239 1f6: 52 07 IF CC R2 = P2;
243 1fe: c2 07 IF CC P0 = P2;
250 20c: 96 07 IF CC P2 = R6;
[all …]
Dload.d27 4a: 02 68 P2 = 0x0 \(X\);.*
42 70: 96 af SP = \[P2 \+ 0x38\];
80 c0: 51 8e R1 = W\[P1 \+\+ P2\] \(X\);
94 d4: da 82 R3.L = W\[P2 \+\+ P3\];
99 da: 90 98 R0 = B\[P2--\] \(Z\);
Dshift.d9 2: ea 45 P2 = \(P2 \+ P5\) << 0x2;
15 a: 0a 5c P0 = P2 \+ \(P1 << 0x1\);
41 56: d1 44 P1 = P2 >> 0x2;
Dflow2.d10 4: 52 00 JUMP \(P2\);
18 14: 82 00 JUMP \(PC \+ P2\);
66 7e: 62 00 CALL \(P2\);
72 8a: 72 00 CALL \(PC \+ P2\);
Dparallel.d32 60: 10 cc 3f 00 A0 = ABS A0 \|\| P2 = \[SP \+ 0x3c\] \|\| R0 = \[I0\];
50 a8: 05 cc 01 98 R4.L = R0 \+ R1 \(RND20\) \|\| B\[P2\] = R0 \|\| R5.L = W\[I2--\];
62 d8: 25 cc 0a 44 R2.H = R1 - R2 \(RND12\) \|\| R1 = B\[P2\] \(Z\) \|\| W\[I2\+\+\] = R4.H;
74 108: 07 cc 13 4a R5 = MIN \(R2, R3\) \|\| B\[P2\] = R2 \|\| R0 = \[I1\+\+\];
94 158: 20 ca 68 26 R1.L = R5.H \* R0.H \(S2RND\) \|\| B\[P2\] = R3 \|\| R2 = \[I0\+\+\];
110 198: 1c cb 3e 80 R1 = R7.H \* R6.L \(M, IS\) \|\| R4 = B\[P2\] \(X\) \|\| \[I0 \+\+ M0\] = R2;
122 1c8: 03 c8 21 0c A0 \+= R4.H \* R1.L \|\| R5 = B\[P2\] \(Z\) \|\| \[I1 \+\+ M1\] = R7;
214 338: 05 ce 07 80 R0.L = SIGNBITS R7.H \|\| R1 = W\[P2\+\+\] \(X\) \|\| \[I2\] = R0;
216 340: 06 ce 00 06 R3.L = SIGNBITS A0 \|\| R2 = W\[P2\+\+\] \(X\) \|\| \[I3\] = R0;
218 348: 06 ce 00 4e R7.L = SIGNBITS A1 \|\| R3 = W\[P2\+\+\] \(Z\) \|\| \[I0\] = R1;
[all …]
Dload.s30 P2 = 0 (x); define
49 SP = [P2 +56];
94 R1 = W [ P1 ++ P2] (X);

12