Searched refs:RegMMX (Results 1 – 7 of 7) sorted by relevance
| /toolchain/binutils/binutils-2.27/opcodes/ |
| D | i386-reg.tbl | 175 mm0, RegMMX, 0, 0, 29, 41
176 mm1, RegMMX, 0, 1, 30, 42
177 mm2, RegMMX, 0, 2, 31, 43
178 mm3, RegMMX, 0, 3, 32, 44
179 mm4, RegMMX, 0, 4, 33, 45
180 mm5, RegMMX, 0, 5, 34, 46
181 mm6, RegMMX, 0, 6, 35, 47
182 mm7, RegMMX, 0, 7, 36, 48
|
| D | i386-opc.tbl | 934 // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's
945 …No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX }
946 …wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX }
947 …MX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg32|Dword|Unspe…
948 …drm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegMMX, Reg64|Qword|BaseI…
964 …o_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
965 …lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|D…
966 …No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX }
967 …rm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegMMX, Reg64|Unspecified…
979 …o_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
[all …]
|
| D | i386-opc.h | 661 RegMMX, enumerator
|
| D | i386-gen.c | 599 BITFIELD (RegMMX),
|
| D | ChangeLog-2007 | 827 (RegMMX): Likewise.
|
| /toolchain/binutils/binutils-2.27/gas/ |
| D | ChangeLog-9697 | 1486 * config/tc-i386.c (pi): Check for RegMMX.
1523 * config/tc-i386.h (RegMMX): Define.
1525 (type_names): Add RegMMX.
1526 (md_assemble): Handle RegMMX.
|
| D | ChangeLog-0001 | 3742 SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem):
|