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Searched refs:SC (Results 1 – 12 of 12) sorted by relevance

/toolchain/binutils/binutils-2.27/opcodes/
Drl78-decode.opc118 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
216 ID(add); DR(A); SC(IMMU(1)); Fzac;
228 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
248 ID(addc); DR(A); SC(IMMU(1)); Fzac;
260 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
271 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
280 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
300 ID(and); DR(A); SC(IMMU(1)); Fz;
312 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
438 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
[all …]
Drl78-decode.c119 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c) macro
258 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; in rl78_decode_opcode()
320 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
352 ID(add); DR(A); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
412 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
504 ID(mov); DM(B, IMMU(2)); SC(IMMU(1)); in rl78_decode_opcode()
519 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
551 ID(addc); DR(A); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
611 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac; in rl78_decode_opcode()
664 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac; in rl78_decode_opcode()
[all …]
Drx-decode.opc113 #define SC(i) OP (1, RX_Operand_Immediate, 0, i)
285 ID(mov); DR(rdst); SC(IMM (1)); F_____;
294 SC(IMM(im));
299 SC(IMMex(im));
304 ID(mov); DR(rdst); SC(immm); F_____;
307 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
392 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
395 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
401 ID(rtsd); SC(IMM(1) * 4);
404 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
[all …]
Dmsp430-decode.opc85 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
202 SC (0);
221 SC (1);
233 SC (4);
236 SC (2);
252 SC (x);
256 SC (8);
259 SC (-1);
430 PC+X *as* the address. So we use SC to use the address, not the
432 ID (MSO_jmp); SC (pc + raddr + msp430->n_bytes);
[all …]
Dmsp430-decode.c86 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c) macro
203 SC (0); in encode_as()
222 SC (1); in encode_as()
234 SC (4); in encode_as()
237 SC (2); in encode_as()
253 SC (x); in encode_as()
257 SC (8); in encode_as()
260 SC (-1); in encode_as()
549 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr); in msp430_decode_opcode()
573 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr); in msp430_decode_opcode()
[all …]
Drx-decode.c114 #define SC(i) OP (1, RX_Operand_Immediate, 0, i) macro
3827 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____; in rx_decode_opcode()
3872 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); in rx_decode_opcode()
4401 ID(add); SC(immm); DR(rdst); F_OSZC; in rx_decode_opcode()
4437 DR(rdst); SC(immm); F_____; in rx_decode_opcode()
4464 ID(and); SC(immm); DR(rdst); F__SZ_; in rx_decode_opcode()
4491 ID(or); SC(immm); DR(rdst); F__SZ_; in rx_decode_opcode()
4518 ID(mov); DR(rdst); SC(immm); F_____; in rx_decode_opcode()
4535 ID(rtsd); SC(IMM(1) * 4); in rx_decode_opcode()
4738 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC; in rx_decode_opcode()
[all …]
Dia64-waw.tbl47 CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 5.8.3.4, "End of External Interrupt Registe…
63 CR[IVR]; IC:none; IC:none; SC
64 CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC
83 InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC
90 MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
Dia64-raw.tbl48 CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 5.8.3.4, "End of External Interrupt Register (EOI - …
70 CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 5.8.3.2, "External Interrupt Vector Register (IVR …
71 CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 5.8.3.1, "Local ID (LID - CR64)" on page …
76 CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l+17, ssm+17; SC Section 5.8.3.3, "Task Priority Register …
121 PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC Section 7.2.1, "Generic Performance Counter Re…
Dppc-opc.c2548 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) macro
4189 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4190 {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
4191 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4192 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4193 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4194 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
/toolchain/benchmark/panorama_input/
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