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Searched refs:SR (Results 1 – 25 of 76) sorted by relevance

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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/msp430/
Derrata_warns.l9 [^:]*:18: Warning: CPU11: PC is destinstion of SR altering instruction
10 [^:]*:19: Warning: CPU11: PC is destinstion of SR altering instruction
11 [^:]*:20: Warning: CPU11: PC is destinstion of SR altering instruction
13 [^:]*:21: Warning: CPU11: PC is destinstion of SR altering instruction
14 [^:]*:22: Warning: CPU11: PC is destinstion of SR altering instruction
15 [^:]*:23: Warning: CPU11: PC is destinstion of SR altering instruction
16 [^:]*:24: Warning: CPU11: PC is destinstion of SR altering instruction
17 [^:]*:25: Warning: CPU11: PC is destinstion of SR altering instruction
18 [^:]*:26: Warning: CPU11: PC is destinstion of SR altering instruction
19 [^:]*:30: Warning: CPU11: PC is destinstion of SR altering instruction
[all …]
Dbad.s32 BIC #8, SR
33 BIS #8, SR
34 MOV.W #1, SR
Derrata_fixes.s8 # CPU11: The SR flags can be left in a bogus state after writing to the PC
9 # Instructions that do not set the SR flags are unaffected.
Derrata_warns.s17 # CPU11: The SR flags can be left in a bogus state after writing to the PC
33 #CPU13: Arithmetic operations with SR as the destination do not work.
/toolchain/binutils/binutils-2.27/opcodes/
Dm32r-opc.c225 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
231 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
237 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
243 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
249 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
255 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
261 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
267 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
279 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
285 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
[all …]
Drx-decode.opc114 #define SR(r) OP (1, RX_Operand_Register, r, 0)
332 ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
344 ID(mov); sBWL (sz); SR(rsrc); F_____;
365 ID(popm); SR(dsta); S2R(dstb); F_____;
368 ID(pushm); SR(dsta); S2R(dstb); F_____;
374 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
422 ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
440 ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
458 ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
461 ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_;
[all …]
Drl78-decode.opc119 #define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
126 #define SCY() SR(PSW); SB(0)
225 ID(add); DRB(reg); SR(A); Fzac;
254 ID(addc); DRB(reg); SR(A); Fzac;
306 ID(and); DRB(reg); SR(A); Fz;
320 ID(and); DCY(); SR(A); SB(bit);
334 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
337 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
340 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
343 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
[all …]
Dm32r-opinst.c46 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
53 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
59 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
66 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
81 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
89 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
98 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
201 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
208 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
215 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
[all …]
Dxc16x-opc.c749 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
755 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
821 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
827 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1145 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1151 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1157 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1541 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1577 { { MNEM, ' ', OP (DR), ',', '[', OP (SR), ']', 0 } },
1583 { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), ']', 0 } },
[all …]
Drl78-decode.c120 #define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0) macro
127 #define SCY() SR(PSW); SB(0)
288 ID(xch); DR(A); SR(X); in rl78_decode_opcode()
454 ID(mov); W(); DRW(ra); SR(AX); in rl78_decode_opcode()
489 ID(mov); DM(B, IMMU(2)); SR(A); in rl78_decode_opcode()
694 ID(mov); DM(C, IMMU(2)); SR(A); in rl78_decode_opcode()
864 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); in rl78_decode_opcode()
902 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); in rl78_decode_opcode()
940 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F); in rl78_decode_opcode()
1479 ID(mov); DM(BC, IMMU(2)); SR(A); in rl78_decode_opcode()
[all …]
Dmsp430-decode.opc86 #define SR(r) OP (1, MSP430_Operand_Register, r, 0)
152 PC SP SR CG
176 case 2: /* (SR) -> Absolute. */
205 SR (reg);
216 case 2: /* SR -> Absolute. */
458 ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
463 ID (MSO_mov); SR (srcr); DM (dstr, IMMS(2));
497 ID (MSO_mov); SR (srcr); DR (dstr);
502 ID (MSO_cmp); SR (srcr); DR (dstr);
508 ID (MSO_add); SR (srcr); DR (dstr);
[all …]
Drx-decode.c115 #define SR(r) OP (1, RX_Operand_Register, r, 0) macro
415 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC; in rx_decode_opcode()
476 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC; in rx_decode_opcode()
3906 ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC; in rx_decode_opcode()
3964 ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC; in rx_decode_opcode()
4347 ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC; in rx_decode_opcode()
4374 ID(sub); S2C(immm); SR(rdst); F_OSZC; in rx_decode_opcode()
4564 ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC; in rx_decode_opcode()
4604 ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC; in rx_decode_opcode()
4644 ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC; in rx_decode_opcode()
[all …]
Dmsp430-decode.c87 #define SR(r) OP (1, MSP430_Operand_Register, r, 0) macro
206 SR (reg); in encode_as()
475 ID (MSO_rrc); DR (dstr); SR (dstr); in msp430_decode_opcode()
501 ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2)); in msp430_decode_opcode()
525 ID (MSO_mov); SR (srcr); DM (dstr, IMMS(2)); in msp430_decode_opcode()
648 ID (MSO_mov); SR (srcr); DR (dstr); in msp430_decode_opcode()
672 ID (MSO_cmp); SR (srcr); DR (dstr); in msp430_decode_opcode()
697 ID (MSO_add); SR (srcr); DR (dstr); in msp430_decode_opcode()
722 ID (MSO_sub); SR (srcr); DR (dstr); in msp430_decode_opcode()
769 ID (MSO_rra); DR (dstr); SR (dstr); in msp430_decode_opcode()
[all …]
/toolchain/binutils/binutils-2.27/cpu/
Dor1kcommon.cpu168 (SYS SR #x011 "Supervision Regsiter")
240 (SYS SR SM 0 0 "supervisor mode bit")
241 (SYS SR TEE 1 1 "tick timer exception enabled bit")
242 (SYS SR IEE 2 2 "interrupt exception enabled bit")
243 (SYS SR DCE 3 3 "data cache enabled bit")
244 (SYS SR ICE 4 4 "insn cache enabled bit")
245 (SYS SR DME 5 5 "data MMU enabled bit")
246 (SYS SR IME 6 6 "insn MMU enabled bit")
247 (SYS SR LEE 7 7 "little endian enabled bit")
248 (SYS SR CE 8 8 "CID enable bit")
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/sh64/
Dcreg-1.s27 getcon SR,r2
63 putcon r2,SR
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mmix/
Dlist-insns.s80 SR $12,$20,205
81 SR $2,$223,$11
/toolchain/binutils/binutils-2.27/gas/doc/
Dc-msp430.texi53 Do not update the @code{SR} and the @code{PC} in the same instruction.
57 Do not use an arithmetic instruction to modify the @code{SR}.
83 SR}, @code{BIS #8, SR} or @code{MOV.W <>, SR}) must be
190 Register names @samp{PC}, @samp{SP} and @samp{SR} cannot be used as register names
Dc-sh.texi301 ldc Rn,SR mov.w @@Rm+,Rn
304 ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
314 or #imm,R0 stc.l SR,@@-Rn
336 stc SR,Rn
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/arch/
Dsh.s45 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
48 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
125 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
128 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…
Dsh2a-nofpu-or-sh4-nommu-nofpu.s51 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
54 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
135 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
138 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…
Dsh2a-nofpu-or-sh3-nommu.s54 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
57 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
135 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
138 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-sh/arch/
Dsh.s45 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
48 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
125 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
128 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…
Dsh2.s58 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
61 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
138 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
141 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…
Dsh2a-nofpu-or-sh4-nommu-nofpu.s51 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
54 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
135 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
138 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…
Dsh2a-nofpu-or-sh3-nommu.s54 …ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4…
57 …ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX…
135 …stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0…
138 …stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX…

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