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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/epiphany/
Dregression.s130 SUB R0,R0,#0x4 ;//restoring R0
132 SUB R0,R0,#0x4 ;//restoring R0
136 SUB R0,R0,#0x4 ;//restoring R0
140 PM: SUB R0,R0,#0x4 ;//restoring R0
142 SUB R0,R0,#0x4 ;//restoring R0
144 SUB R0,R0,#0x4 ;//restoring R0
161 SUBLAB: SUB R63,R2,#1; //2+1=1
197 SUB3LAB: SUB R63,R6,R4 ; //6-4=2
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Darmv8-a-it-bad.l15 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
16 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
17 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
18 …ining 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
Dsp-pc-usage-t.s90 @ SUB (sp minus immediate).
100 @ SUB (sp minus register).
Dgroup-reloc-alu.s30 @ The following should cause the insns to be switched to SUB(S).
Daddthumb2err.s6 # Test of invalid operands for ADD{S} and SUB{S} instructions
Dthumb2_bad_reg.s668 @ SUB (immediate)
671 sub.w r0, r13, #1 @ SUB (SP minus immediate)
675 subw r0, r13, #1 @ SUB (SP minus immediate)
677 @ SUB (register)
680 sub.w r0, r13, r1 @ SUB (SP minus register)
684 @ SUB (SP minus immediate)
689 @ SUB (SP minus register)
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/metag/
Dmetafpu21ext.s85 FD SUB FX.0,FX.2,FX.4
86 F SUB FX.3,FX.1,FX.0
87 FL SUB FX.6,FX.4,FX.2
88 FDI SUB FX.0,FX.2,FX.4
89 FI SUB FX.3,FX.1,FX.0
90 FLI SUB FX.6,FX.4,FX.2
Dmetafpu21ext.d93 .*: f1008921 FD SUB FX\.0,FX\.2,FX\.4
94 .*: f1184101 F SUB FX\.3,FX\.1,FX\.0
95 .*: f1310541 FL SUB FX\.6,FX\.4,FX\.2
96 .*: f10089a1 FDI SUB FX\.0,FX\.2,FX\.4
97 .*: f1184181 FI SUB FX\.3,FX\.1,FX\.0
98 .*: f13105c1 FLI SUB FX\.6,FX\.4,FX\.2
Dmetafpu21.s232 F SUB FX.0,D0.7,D0Re0
235 F SUB FX.1,D0Re0,A1LbP
238 F SUB FX.1,D0.7,D0.7
241 F SUB FX.2,D0Re0,D1Re0
244 F SUB FX.2,D0.7,D1.7
247 F SUB FX.3,D0Re0,RD
250 F SUB FX.3,D0.7,A0FrP
253 F SUB FX.4,D0.7,D0Re0
256 F SUB FX.5,D0Re0,A1LbP
259 F SUB FX.5,D0.7,D0.7
[all …]
Dmetacore12.s468 SUB D0Re0,D0Re0,A1LbP
469 SUB D0Re0,D0Re0,D1.7
470 SUB D0Re0,D0.7,D0Re0
471 SUB D0Re0,D0.7,A0.7
474 SUB D0.7,D0.7,D1.7 define
475 SUB D1Re0,D1Re0,D1.7
476 SUB D1Re0,D1Re0,RD
477 SUB D1Re0,D1.7,D1.7
481 SUB D1.7,D1.7,A0FrP define
668 SUB TXENABLE,D0Re0,#0x7f
[all …]
Dmetafpu21.d240 .*: 1401c120 F SUB FX\.0,D0\.7,D0Re0
243 .*: 14080321 F SUB FX\.1,D0Re0,A1LbP
246 .*: 1409cf20 F SUB FX\.1,D0\.7,D0\.7
249 .*: 14101121 F SUB FX\.2,D0Re0,D1Re0
252 .*: 1411df21 F SUB FX\.2,D0\.7,D1\.7
255 .*: 14182121 F SUB FX\.3,D0Re0,RD
258 .*: 1419f321 F SUB FX\.3,D0\.7,A0FrP
261 .*: 1421c120 F SUB FX\.4,D0\.7,D0Re0
264 .*: 14280321 F SUB FX\.5,D0Re0,A1LbP
267 .*: 1429cf20 F SUB FX\.5,D0\.7,D0\.7
[all …]
Dmetacore21.s362 SUB D0Re0,D0.7,A0FrP
364 SUB D0.7,D0Re0,A0FrP define
365 SUB D0.7,D0.7,D1Re0 define
368 SUB D1Re0,D1.7,A1LbP
369 SUB D1.7,D1Re0,D1Re0 define
370 SUB D1.7,D1Re0,D0Re0 define
371 SUB D1.7,D1Re0,A0.7 define
372 SUB D1.7,D1.7,RD define
373 SUB D0Re0,D0Re0,#-0x8000
374 SUB D0.7,D0.7,#0x7fff define
[all …]
Dmetacore21.d370 .*: 1001f201 SUB D0Re0,D0\.7,A0FrP
372 .*: 10383201 SUB D0\.7,D0Re0,A0FrP
373 .*: 1039d001 SUB D0\.7,D0\.7,D1Re0
376 .*: 1101c201 SUB D1Re0,D1\.7,A1LbP
377 .*: 11380000 SUB D1\.7,D1Re0,D1Re0
378 .*: 11381001 SUB D1\.7,D1Re0,D0Re0
379 .*: 11383e01 SUB D1\.7,D1Re0,A0\.7
380 .*: 1139e001 SUB D1\.7,D1\.7,RD
381 .*: 12040002 SUB D0Re0,D0Re0,#-32768
382 .*: 123bfff8 SUB D0\.7,D0\.7,#0x7fff
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Daddsub.s176 .irp op, ADD, ADDS, SUB, SUBS
201 .irp op, ADD, ADDS, SUB, SUBS
216 .irp op, SUB, SUBS
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mmix/
Dlist-insns.s61 SUB $12,$223,$11
62 SUB $122,$203,205
Dlist-insns.l67 61 00d8 240CDF0B SUB \$12,\$223,\$11
68 62 00dc 257ACBCD SUB \$122,\$203,205
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/
Dinsns16-d-unit.s25 ; op = 1 | SUB (.unit) src1, src2, dst (src1 = dst, dst = src1 - src2
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-metag/
Dstub_shared.s15 SUB A0StP,A0FrP,#(8)
Dshared.s21 SUB A0StP,A0FrP,#(8)
Dstub_shared.d34 .*: 8e004226 SUB A0StP,A0FrP,#0x8
Dshared.d39 .*: 8e004226 SUB A0StP,A0FrP,#0x8
/toolchain/binutils/binutils-2.27/opcodes/
Dm88k-dis.c129 …{0xf4007400,"sub ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0…
130 …{0xf4007600,"sub.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0…
131 …{0xf4007500,"sub.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0…
132 …{0xf4007700,"sub.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0…
142 …{0x74000000,"sub ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,SUB, i16bit,1,0,1,0…
/toolchain/binutils/binutils-2.27/zlib/doc/
Dtxtvsbin.txt44 7 (BEL), 8 (BS), 11 (VT), 12 (FF), 26 (SUB), 27 (ESC).
65 7 (BEL), 8 (BS), 11 (VT), 12 (FF), 26 (SUB) and 27 (ESC); but these
/toolchain/binutils/binutils-2.27/include/opcode/
Dm88k.h261 #define SUB ADD+4 macro
/toolchain/binutils/binutils-2.27/gas/config/
Drx-parse.y167 %token SMOVU SSTR STNZ STOP STZ SUB SUNTIL SWHILE
346 | SUB '#' EXPR ',' REG
837 | SUB { sub_op = 0; } op_subadd
1266 OPC(SUB),

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