Searched refs:TIC80_VECTOR (Results 1 – 4 of 4) sorted by relevance
/toolchain/binutils/binutils-2.27/opcodes/ |
D | tic80-opc.c | 1136 …{"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_… 1137 …{"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI… 1138 …{"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_… 1139 …{"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI… 1140 …{"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_… 1151 …{"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC8… 1152 …{"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC8… 1153 …{"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC8… 1154 …{"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC8… 1155 …{"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC8… [all …]
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D | tic80-dis.c | 289 if (opcode->flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) in print_instruction()
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/toolchain/binutils/binutils-2.27/include/opcode/ |
D | tic80.h | 251 #define TIC80_VECTOR 01 /* Is a vector instruction */ macro
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D | ChangeLog-9103 | 2003 (TIC80_VECTOR): Define a flag bit for the flags. This one means
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