| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| D | group-reloc-ldc-encoding-bad.l | 2 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
3 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
4 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
5 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
6 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
7 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
8 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
9 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
10 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
11 [^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[all …]
|
| D | armv8-2-fp16-scalar-bad.l | 6 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
7 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
8 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
9 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
10 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
11 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
12 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
13 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
14 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
15 .*:79: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTAB…
[all …]
|
| D | neon-cond-bad.l | 2 [^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1'
4 [^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0'
6 [^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'
8 [^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'
10 [^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'
12 [^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'
14 [^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
16 [^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
18 [^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
20 [^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
[all …]
|
| D | srs-arm.l | 2 [^:]*:12: Error: SRS base register must be r13 -- `srsdb r4,#13'
4 [^:]*:14: Error: SRS base register must be r13 -- `srsia r4,#13'
6 [^:]*:24: Error: SRS base register must be r13 -- `srsea r4,#13'
8 [^:]*:26: Error: SRS base register must be r13 -- `srsfa r4,#13'
10 [^:]*:30: Error: SRS base register must be r13 -- `srs r4,#13'
|
| D | thumb2_ldr_immediate_highregs_armv6t2.s | 5 # These must be encoded into mov.w despite constant and register being
15 # These shall be encoded into mov.w since register cannot be encoded in
23 # These shall be encoded into movw since immediate cannot be encoded
27 # These should be encoded as ldr since mov immediate is unpredictable
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/ |
| D | predicate-bad-2.l | 3 [^:]*:5: Error: instruction 'nop' cannot be predicated
4 [^:]*:6: Error: instruction 'nop' cannot be predicated
5 [^:]*:7: Error: instruction 'nop' cannot be predicated
6 [^:]*:8: Error: instruction 'nop' cannot be predicated
7 [^:]*:9: Error: instruction 'nop' cannot be predicated
8 [^:]*:10: Error: instruction 'nop' cannot be predicated
10 [^:]*:11: Error: instruction 'nop' cannot be predicated
11 [^:]*:12: Error: instruction 'nop' cannot be predicated
12 [^:]*:13: Error: instruction 'nop' cannot be predicated
13 [^:]*:14: Error: instruction 'nop' cannot be predicated
[all …]
|
| D | predicate-bad-3.l | 2 [^:]*:5: Error: instruction 'nop' cannot be predicated
3 [^:]*:6: Error: instruction 'nop' cannot be predicated
4 [^:]*:7: Error: instruction 'addab' cannot be predicated
5 [^:]*:8: Error: instruction 'addah' cannot be predicated
6 [^:]*:9: Error: instruction 'addaw' cannot be predicated
7 [^:]*:10: Error: instruction 'callp' cannot be predicated
8 [^:]*:11: Error: instruction 'addsub' cannot be predicated
9 [^:]*:12: Error: instruction 'addsub2' cannot be predicated
10 [^:]*:13: Error: instruction 'cmpy' cannot be predicated
11 [^:]*:14: Error: instruction 'cmpyr' cannot be predicated
[all …]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ia64/ |
| D | invalid-ar.l | 2 .*:2: Error: AR 0 can only be accessed by M-unit
3 .*:3: Error: AR 1 can only be accessed by M-unit
4 .*:4: Error: AR 2 can only be accessed by M-unit
5 .*:5: Error: AR 3 can only be accessed by M-unit
6 .*:6: Error: AR 4 can only be accessed by M-unit
7 .*:7: Error: AR 5 can only be accessed by M-unit
8 .*:8: Error: AR 6 can only be accessed by M-unit
9 .*:9: Error: AR 7 can only be accessed by M-unit
10 .*:10: Error: AR 8 can only be accessed by M-unit
11 .*:11: Error: AR 9 can only be accessed by M-unit
[all …]
|
| D | index.l | 2 .*.s:6: Error: [Ii]ndex must be a general register
3 .*.s:7: Error: [Ii]ndex must be a general register
4 .*.s:8: Error: [Ii]ndex must be a general register
5 .*.s:9: Error: [Ii]ndex must be a general register
6 .*.s:13: Error: [Ii]ndirect register index must be a general register
7 .*.s:14: Error: [Ii]ndirect register index must be a general register
8 .*.s:15: Error: [Ii]ndirect register index must be a general register
9 .*.s:16: Error: [Ii]ndirect register index must be a general register
10 .*.s:20: Error: [Ii]ndex can only be applied to rotating or indirect registers
11 .*.s:21: Error: [Ii]ndex can only be applied to rotating or indirect registers
[all …]
|
| D | unwind-bad.l | 2 .*:8: Error: First operand to \.save\.g must be a positive 4-bit constant
3 .*:10: Error: First operand to \.save\.g must be a positive 4-bit constant
4 .*:12: Error: First operand to \.save\.g must be a positive 4-bit constant
7 .*:20: Error: Operand to \.save\.f must be a positive 20-bit constant
8 .*:22: Error: Operand to \.save\.f must be a positive 20-bit constant
9 .*:24: Error: Operand to \.save\.f must be a positive 20-bit constant
12 .*:32: Error: First operand to \.save\.b must be a positive 5-bit constant
13 .*:34: Error: First operand to \.save\.b must be a positive 5-bit constant
14 .*:36: Error: First operand to \.save\.b must be a positive 5-bit constant
17 .*:44: Error: Operand 2 to \.spillreg must be a writable register
[all …]
|
| D | opc-a-err.l | 3 .*:2: Error: Operand 2 of `adds' should be a 14-bit .*
5 .*:5: Error: Operand 2 of `addl' should be a 22-bit .*
7 .*:8: Error: Operand 2 of `sub' should be .*
9 .*:11: Error: Operand 2 of `and' should be .*
11 .*:14: Error: Operand 2 of `or' should be .*
13 .*:17: Error: Operand 2 of `xor' should be .*
15 .*:20: Error: Operand 2 of `andcm' should be .*
17 .*:23: Error: Operand [34] of `cmp4.lt.or' should be r0
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/cris/ |
| D | ccr.d | 10 [ ]+4:[ ]+bff5[ ]+setf[ ]+cvznxi[be][dm]
11 [ ]+6:[ ]+fff5[ ]+clearf[ ]+cvznxi[be][dm]
30 [ ]+2c:[ ]+b045[ ]+setf[ ]+[be]
31 [ ]+2e:[ ]+f045[ ]+clearf[ ]+[be]
50 [ ]+54:[ ]+f0f5[ ]+clearf[ ]+xi[be][dm]
51 [ ]+56:[ ]+b0f5[ ]+setf[ ]+xi[be][dm]
52 [ ]+58:[ ]+f0f5[ ]+clearf[ ]+xi[be][dm]
53 [ ]+5a:[ ]+b0f5[ ]+setf[ ]+xi[be][dm]
54 [ ]+5c:[ ]+fa55[ ]+clearf[ ]+vnx[be]
55 [ ]+5e:[ ]+ba55[ ]+setf[ ]+vnx[be]
[all …]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ |
| D | iamcu-1.d | 10 [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
11 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
13 [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
14 [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
15 [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
16 [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
18 [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
19 [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
34 [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
35 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | x86-64-nops-5.d | 11 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
16 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
21 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
26 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
31 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
36 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
41 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
46 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
51 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
56 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | x86-64-nops-5-k8.d | 12 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
17 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
22 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
27 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
32 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
37 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
42 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
47 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
52 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
57 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | nops-5.d | 9 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
14 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
19 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
24 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
29 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
34 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
39 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
44 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
49 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
54 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | nops-5-i686.d | 11 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
16 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
21 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
26 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
31 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
36 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
41 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
46 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
51 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
56 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | i386.d | 13 [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
14 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
16 [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
17 [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
18 [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
19 [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
21 [ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
22 [ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
43 [ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
44 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | i386-intel.d | 14 [ ]*[a-f0-9]+: 66 0f be f0 movsx si,al
15 [ ]*[a-f0-9]+: 0f be f0 movsx esi,al
17 [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\]
18 [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\]
19 [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\]
20 [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\]
22 [ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\]
23 [ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\]
44 [ ]*[a-f0-9]+: 66 0f be f0 movsx si,al
45 [ ]*[a-f0-9]+: 0f be f0 movsx esi,al
[all …]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ilp32/ |
| D | x86-64-nops-5.d | 10 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
15 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
20 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
25 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
30 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
35 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
40 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
45 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
50 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
55 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| D | x86-64-nops-5-k8.d | 11 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
16 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
21 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
26 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
31 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
36 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
41 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
46 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
51 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
56 [ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[all …]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/msp430/ |
| D | bad.l | 8 [^:]*:16: Warning: a NOP might be needed here because of successive changes in interrupt state
9 [^:]*:16: Warning: a NOP might be needed before the EINT
10 [^:]*:25: Warning: a NOP might be needed here because of successive changes in interrupt state
11 [^:]*:25: Warning: a NOP might be needed before the EINT
12 [^:]*:29: Warning: a NOP might be needed here because of successive changes in interrupt state
13 [^:]*:31: Warning: a NOP might be needed here because of successive changes in interrupt state
14 [^:]*:32: Warning: a NOP might be needed here because of successive changes in interrupt state
15 [^:]*:33: Warning: a NOP might be needed here because of successive changes in interrupt state
16 [^:]*:34: Warning: a NOP might be needed here because of successive changes in interrupt state
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| D | bltzal.l | 2 .*:3: Error: the source register must not be \$31.*
3 .*:4: Error: the source register must not be \$31.*
4 .*:6: Error: the source register must not be \$31.*
5 .*:7: Error: the source register must not be \$31.*
6 .*:9: Error: the source register must not be \$31.*
7 .*:10: Error: the source register must not be \$31.*
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/ |
| D | e500mc.d | 14 10: (7c 09 57 be|be 57 09 7c) icbiep r9,r10
26 40: (7c 22 18 be|be 18 22 7c) lbepx r1,r2,r3
30 50: (7d ae 7c be|be 7c ae 7d) lfdepx f13,r14,r15
31 54: (7e 11 91 be|be 91 11 7e) stbepx r16,r17,r18
35 64: (7f 9d f5 be|be f5 9d 7f) stfdepx f28,r29,r30
44 88: (7f be ff 46|46 ff be 7f) stfddx f29,r30,r31
|
| /toolchain/binutils/binutils-2.27/libiberty/ |
| D | at-file.texi | 1 @c This file is designed to be included in manuals that use
7 does not exist, or cannot be read, then the option will be treated
11 character may be included in an option by surrounding the entire
13 backslash) may be included by prefixing the character to be included
15 @@@var{file} options; any such options will be processed recursively.
|