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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
Dmips64-mips3d.l2 .*:150: Warning: condition code register should be even for bc1any2f, was 1
3 .*:152: Warning: condition code register should be even for bc1any2t, was 3
4 .*:154: Warning: condition code register should be 0 or 4 for bc1any4f, was 1
5 .*:156: Warning: condition code register should be 0 or 4 for bc1any4t, was 2
Dmipsr6@mips5-fp.l2 .*:4: Warning: condition code register should be even for c.eq.ps, was 3
3 .*:5: Warning: condition code register should be even for movf.ps, was 3
Dmips5-fp.l2 .*:61: Warning: condition code register should be even for c.eq.ps, was 3
3 .*:62: Warning: condition code register should be even for movf.ps, was 3
Dset-arch.l2 .*:146: Warning: condition code register should be even for c.eq.ps, was 3
3 .*:147: Warning: condition code register should be even for movf.ps, was 3
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Darm-it-auto.s30 @Same, reverted condition:
81 @ite eq - testing condition change (eq -> gt)
85 @ite gt (group shall finish due to another condition change)
Darm-it-bad.l2 [^:]*:8: Error: incorrect condition in IT block -- `moveq r0,r1'
Dfpa-mem.s29 # condition codes
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-aarch64/
Demit-relocs-309.s1 # R_AARCH64_GOT_LD_PREL19 must satisfy condition:
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-mmix/
Db-bend1.d9 # This test depend on that the non-at-end condition is tested before
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/cris/
Dscc.s25 ; Add new condition names here, not above.
/toolchain/binutils/binutils-2.27/include/opcode/
Dmsp430-decode.h87 unsigned char condition : 3; member
Drl78.h143 unsigned char condition : 3; member
/toolchain/binutils/binutils-2.27/cpu/
Diq2000m.cpu131 (dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI)
137 (dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
143 (dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI)
149 (dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
155 (dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI)
161 (dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
167 (dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI)
173 (dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
Dfrv.cpu1951 (dnf f-CCi "condition register" () 11 3)
1959 (dnf f-ICCi_1 "condition register" () 11 2)
1960 (dnf f-ICCi_2 "condition register" () 26 2)
1961 (dnf f-ICCi_3 "condition register" () 1 2)
1962 (dnf f-FCCi_1 "condition register" () 11 2)
1963 (dnf f-FCCi_2 "condition register" () 26 2)
1964 (dnf f-FCCi_3 "condition register" () 1 2)
1965 (dnf f-FCCk "condition register" () 26 2)
1995 (df f-ccond "lr branch condition" () 12 1 UINT #f #f)
2980 ; Integer condition code registers (CCR)
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Dcris.cpu520 (define-pmacro cc-condition (not cbit))
521 (define-pmacro cs-condition cbit)
522 (define-pmacro ne-condition (not zbit))
523 (define-pmacro eq-condition zbit)
524 (define-pmacro vc-condition (not vbit))
525 (define-pmacro vs-condition vbit)
526 (define-pmacro pl-condition (not nbit))
527 (define-pmacro mi-condition nbit)
528 (define-pmacro ls-condition (or cbit zbit))
529 (define-pmacro hi-condition (not (or cbit zbit)))
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Dfr30.cpu148 (dnf f-cc "condition code" () 4 4)
268 ; insn-cc: condition codes
383 (comment "condition code bits")
390 (comment "system condition bits")
513 (dnop cc "condition codes" () h-uint f-cc)
526 (dnop ccr "condition code bits" (SEM-ONLY) h-ccr f-nil)
527 (dnop scr "system condition bits" (SEM-ONLY) h-scr f-nil)
1434 (define-pmacro (cond-branch cc condition)
1442 (if condition (set pc label9)))
1450 (if condition (set pc label9))
Dmep-rhcop.cpu236 ; Set branch condition flags to value of code16a[0:3]
237 ; Branch condition flags do not exist yet.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/z8k/
Dret-cc.d3 #name: return on condition code
/toolchain/binutils/binutils-2.27/opcodes/
Ds390-opc.txt25 47 bc RX_URRD "branch on condition" g5 esa,zarch
26 07 bcr RR_UR "branch on condition" g5 esa,zarch
251 a704 brc RI_UP "branch relative on condition" g5 esa,zarch
464 c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
1024 b9f2 locr RRF_U0RR "load on condition 32 bit" z196 zarch
1025 b9f20000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch
1026 b9e2 locgr RRF_U0RR "load on condition 64 bit" z196 zarch
1027 b9e20000 locgr*16 RRF_00RR "load on condition 64 bit" z196 zarch
1028 eb00000000f2 loc RSY_RURD2 "load on condition 32 bit" z196 zarch
1029 eb00000000f2 loc*12 RSY_R0RD "load on condition 32 bit" z196 zarch
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Drl78-dis.c245 PR (PS, "%s", condition_names[oper->condition]); in print_insn_rl78_common()
DChangeLog-20104 * hppa-dis.c (compare_cond_64_names): Change never condition to ",*".
116 condition instructions to cover the condition code mask as well.
384 (float_cc_names): new structure for condition codes.
959 dumping condition, and the initial mapping symbol state.
/toolchain/binutils/binutils-2.27/gas/doc/
Dc-arc.texi418 ARC supports extensible condition codes. This directive defines a new
419 condition code, to be known by the suffix, @var{suffix} and will
420 depend on the value, @var{val} in the condition code.
427 will only execute the @code{add} instruction if the condition code
545 operands. It sets the flags and can be used with a condition code,
Dc-m68hc11.texi439 XX: condition
440 NX: negative of condition XX
453 where @var{XX} is a conditional branch or condition-code test. The full
462 @var{NX}, the opposite condition to @var{XX}. For example, for the
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic4x/
Daddressing.s9 ;; Type B - infix condition branch
41 ;; Type C - infix condition load
/toolchain/binutils/binutils-2.27/gas/
DChangeLog-20105 to determine whether a 64-bit condition is needed for 'A' and 'S'
6 conditions. Default to 32-bit never condition for logical and unit
7 instructions. Add error message for missing branch on bit condition.
40 doubleword completer or doubleword condition is found in an add/sub
41 instruction. Reject match for 'A'/'S' only if there is no condition
757 * config/tc-arm.c (parse_psr): Add condition for matching "APSR" on
930 BAD_PC_ADDRESSING condition.
1080 (cc_names): Update the condition code.
1081 (float_cc_names): Update the condition code for float.
1086 (cc_name): Update to support new condition codes.
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