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Searched refs:cvt (Results 1 – 25 of 33) sorted by relevance

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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dneon-cond-bad-inc.s42 .macro cvt to from dot="." macro
48 cvt s32 f32
49 cvt u32 f32
50 cvt f32 s32
51 cvt f32 u32
Dvfp-neon-syntax-inc.s91 .macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" macro
107 cvt
108 cvt eq
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
Dmips32-sf32.s8 cvt.d.s $f8,$f7
9 cvt.d.w $f8,$f7
10 cvt.s.d $f7,$f8
Dmips32-sf32.d15 0+0010 <[^>]*> 46003a21 cvt.d.s \$f8,\$f7
16 0+0014 <[^>]*> 46803a21 cvt.d.w \$f8,\$f7
17 0+0018 <[^>]*> 462041e0 cvt.s.d \$f7,\$f8
Dmicromips@mips32-sf32.d16 [0-9a-f]+ <[^>]*> 5507 137b cvt\.d\.s \$f8,\$f7
17 [0-9a-f]+ <[^>]*> 5507 337b cvt\.d\.w \$f8,\$f7
18 [0-9a-f]+ <[^>]*> 54e8 1b7b cvt\.s\.d \$f7,\$f8
Ddelay.s4 cvt.d.w $f0,$f0
6 cvt.d.w $f2,$f2
Dmipsr6@mips5-fp.s4 cvt.s.pl $f16, $f18
5 cvt.s.pu $f18, $f20
Dmipsr6@mips5-fp.d10 0+0000 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18
11 0+0004 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20
Ddelay.d16 0+0008 <[^>]*> cvt.d.w \$f0,\$f0
19 0+0014 <[^>]*> cvt.d.w \$f2,\$f2
Dnodelay.d16 0+0004 <[^>]*> cvt.d.w \$f0,\$f0
18 0+000c <[^>]*> cvt.d.w \$f2,\$f2
Dtrunc.d17 0+001c <[^>]*> cvt.w.d \$f4,\$f6
27 0+0044 <[^>]*> cvt.w.s \$f4,\$f6
Dmips5-fp.s39 cvt.ps.s $f12, $f14, $f16
40 cvt.s.pl $f16, $f18
41 cvt.s.pu $f18, $f20
Dr5900.s45 # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
46 # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
Dr5900-full.s49 # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
50 # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
Dmicromips.s3898 cvt.d.l $f0, $f1
3899 cvt.d.l $f30, $f31
3900 cvt.d.l $f2, $f2
3902 cvt.d.s $f0, $f1
3903 cvt.d.s $f30, $f31
3904 cvt.d.s $f2, $f2
3906 cvt.d.w $f0, $f1
3907 cvt.d.w $f30, $f31
3908 cvt.d.w $f2, $f2
3910 cvt.l.s $f0, $f1
[all …]
Dmips5-fp.d45 0+008c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16
46 0+0090 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18
47 0+0094 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20
Dmicromips@mips5-fp.d46 [0-9a-f]+ <[^>]*> 560e 6180 cvt\.ps\.s \$f12,\$f14,\$f16
47 [0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18
48 [0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20
Dmips32-sf32.l6 .*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
Dset-arch.d99 0000016c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16
100 00000170 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18
101 00000174 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20
Dmips64-mips3d.s128 cvt.pw.ps $f4, $f19
130 cvt.ps.pw $f4, $f19
Dmips64-mips3d-incl.d127 0+01c4 <[^>]*> 46c09924 cvt\.pw\.ps \$f4,\$f19
128 0+01c8 <[^>]*> 46809926 cvt\.ps\.pw \$f4,\$f19
Dmips64-mips3d.d124 0+01c4 <[^>]*> 46c09924 cvt\.pw\.ps \$f4,\$f19
125 0+01c8 <[^>]*> 46809926 cvt\.ps\.pw \$f4,\$f19
Dmips16-intermix.s1285 cvt.d.w $f0,$f2
1318 cvt.d.w $f0,$f2
1350 cvt.d.w $f0,$f2
1382 cvt.d.w $f0,$f2
1414 cvt.d.w $f0,$f2
1867 cvt.d.w $f0,$f24
/toolchain/binutils/binutils-2.27/opcodes/
DChangeLog-2006275 (OP_MXC): New function to handle cvt* (convert instructions) between
777 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-mips-elf/
Dmips16-intermix-2.s1285 cvt.d.w $f0,$f2
1318 cvt.d.w $f0,$f2
1350 cvt.d.w $f0,$f2
1382 cvt.d.w $f0,$f2
1414 cvt.d.w $f0,$f2
1867 cvt.d.w $f0,$f24

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