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/toolchain/binutils/binutils-2.27/binutils/
Delfcomm.c64 byte_put_little_endian (unsigned char * field, elf_vma value, int size) in byte_put_little_endian() argument
69 field[7] = (((value >> 24) >> 24) >> 8) & 0xff; in byte_put_little_endian()
70 field[6] = ((value >> 24) >> 24) & 0xff; in byte_put_little_endian()
71 field[5] = ((value >> 24) >> 16) & 0xff; in byte_put_little_endian()
72 field[4] = ((value >> 24) >> 8) & 0xff; in byte_put_little_endian()
75 field[3] = (value >> 24) & 0xff; in byte_put_little_endian()
78 field[2] = (value >> 16) & 0xff; in byte_put_little_endian()
81 field[1] = (value >> 8) & 0xff; in byte_put_little_endian()
84 field[0] = value & 0xff; in byte_put_little_endian()
94 byte_put_big_endian (unsigned char * field, elf_vma value, int size) in byte_put_big_endian() argument
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Delfcomm.h51 #define BYTE_PUT(field, val) byte_put (field, val, sizeof (field)) argument
52 #define BYTE_GET(field) byte_get (field, sizeof (field)) argument
53 #define BYTE_GET_SIGNED(field) byte_get_signed (field, sizeof (field)) argument
/toolchain/binutils/binutils-2.27/bfd/
Dcpu-ia64-opc.c65 if (value >= 1u << self->field[0].bits) in ins_reg()
68 *code |= value << self->field[0].shift; in ins_reg()
75 *valuep = ((code >> self->field[0].shift) in ext_reg()
76 & ((1u << self->field[0].bits) - 1)); in ext_reg()
86 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) in ins_immu()
88 new_insn |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1)) in ins_immu()
89 << self->field[i].shift); in ins_immu()
90 value >>= self->field[i].bits; in ins_immu()
105 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) in ext_immu()
107 bits = self->field[i].bits; in ext_immu()
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Delf-hppa.h587 unsigned int field) in elf_hppa_reloc_final_type() argument
605 switch (field) in elf_hppa_reloc_final_type()
633 switch (field) in elf_hppa_reloc_final_type()
649 switch (field) in elf_hppa_reloc_final_type()
673 switch (field) in elf_hppa_reloc_final_type()
692 switch (field) in elf_hppa_reloc_final_type()
714 switch (field) in elf_hppa_reloc_final_type()
732 switch (field) in elf_hppa_reloc_final_type()
748 switch (field) in elf_hppa_reloc_final_type()
767 switch (field) in elf_hppa_reloc_final_type()
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DChangeLog-989991 * targets.c (struct bfd_target): Add new field
131 value by 4 before storing it back in the field. From
461 get the overflow of the s_nlnno field from the s_nreloc field.
464 field.
505 instead. Don't clear the s_paddr field for an uninitialized data
508 * coffcode.h (coff_mkobject_hook): Set timestamp field in
569 comdat_info field.
576 _bfd_filnmlen field.
664 * coffcode.h (bfd_coff_backend_data): Add _bfd_filnmlen field.
666 (bfd_coff_std_swap_table): Initialize new field.
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DChangeLog-949591 (struct aout_final_link_info): Add includes field.
125 field.
167 * bfd.c (struct _bfd): Add ihex_data field to tdata union.
272 * elf-bfd.h (struct elf_obj_tdata): Add segment_map field.
552 descriptor field to point back to the function code symbol.
665 * libcoff-in.h (coff_link_hash_entry): added toc_offset field
666 (pe_tdata): added real_flags field
669 * libcoff.h (coff_link_hash_entry): added toc_offset field
670 (pe_tdata): added real_flags field
764 * targets.c (bfd_target): Add new field for
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic54x/
Dfield.s2 * test .field directive
6 f1: .field 0ABCh, 14 ; f1=0x0
7 f2: .field 0Ah, 5 ; should align to next word, f2=0x1
8 f3: .field 0Ch, 4 ; should be packed in previous word, f3=0x1
9 f4: .field f3 ; align at word 0x2
10 f5: .field 04321h, 32 ;
11 f6: .field 01111b ; default to 16-bit field
12 f7: .field 3,3
13 f8: .field 69,15 ; align at next word
Dcons.s3 * See also long.s, space.s, field.s
5 .global binary, octal, hex, field
9 field: .field 3, 3 label
10 .field 8, 6
11 .field 16, 5
12 .field 01234h,20
13 .field 01234h,32
Dstruct.s33 BIT7 .field 7 ; bit7 = 64
34 BIT9 .field 9 ; bit9 = 64
35 BIT10 .field 10 ; bit10 = 65
/toolchain/binutils/binutils-2.27/cpu/
Dor1kcommon.cpu216 (define-pmacro (spr-field-info)
217 ((SYS VR REV 5 0 "revision field")
218 (SYS VR CFG 23 16 "configuration template field")
219 (SYS VR VER 31 24 "version field")
231 (SYS UPR CUP 31 24 "custom units present field")
232 (SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field")
257 (SYS SR CID 31 28 "context ID field")
259 (SYS FPCSR RM 2 1 "floating point rounding mode field")
273 spr-field-msbs
274 "SPR field msb positions"
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Diq2000.cpu143 (dnf f-opcode "opcode field" () 31 6)
144 (dnf f-rs "register field Rs" () 25 5)
145 (dnf f-rt "register field Rt" () 20 5)
146 (dnf f-rd "register field Rd" () 15 5)
147 (dnf f-shamt "shift amount field" () 10 5)
148 (dnf f-cp-op "coprocessor op field" () 10 3)
149 (dnf f-cp-op-10 "coprocessor op field for CAM" () 10 5)
150 (dnf f-cp-grp "coprocessor group field" () 7 2)
151 (dnf f-func "function field" () 5 6)
152 (dnf f-imm "immediate field" () 15 16)
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Dmep-avc.cpu87 ; instruction field and operand definitions
88 (dnf f-avc-v3sub4u0 "sub opecode field" (avc-32-isa) 0 4)
89 (dnf f-avc-v1sub4u0 "sub opecode field" (avc-16-isa) 0 4)
90 (dnf f-avc-v3Rn "register field" (avc-32-isa) 4 4)
92 (dnf f-avc-v3CCRn "register field" (avc-32-isa) 4 4)
94 (df f-avc-v3Imm16s4x24e32-hi "split immediate field hi" (avc-32-isa) 4 8 INT #f #f)
95 (df f-avc-v3Imm16s4x24e32-lo "split immediate field lo" (avc-32-isa) 24 8 UINT #f #f)
98 (comment "split immediate field")
109 (dnf f-avc-v3CRn "register field" (avc-32-isa) 4 4)
111 (dnf f-avc-v1CRq "register field" (avc-16-isa) 4 4)
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Dmep.opc118 CGEN_KEYWORD *keyword_table, long *field)
123 err = cgen_parse_keyword (cd, strp, keyword_table, field);
130 *field = value;
144 long *field)
146 return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field);
157 long *field)
159 return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field);
165 CGEN_KEYWORD *keyword_table, long *field)
169 err = cgen_parse_keyword (cd, strp, keyword_table, field);
172 if (*field != 13)
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/toolchain/binutils/binutils-2.27/opcodes/
Daarch64-opc.h223 const aarch64_field *field = &fields[kind]; in gen_sub_field() local
224 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width) in gen_sub_field()
226 ret->lsb = field->lsb + lsb_rel; in gen_sub_field()
235 insert_field_2 (const aarch64_field *field, aarch64_insn *code, in insert_field_2() argument
238 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0 in insert_field_2()
239 && field->lsb + field->width <= 32); in insert_field_2()
240 value &= gen_mask (field->width); in insert_field_2()
241 value <<= field->lsb; in insert_field_2()
252 extract_field_2 (const aarch64_field *field, aarch64_insn code, in extract_field_2() argument
258 value = (code >> field->lsb) & gen_mask (field->width); in extract_field_2()
Dtic6x-dis.c114 tic6x_field_from_fmt (const tic6x_insn_format *fmt, tic6x_insn_field_id field) in tic6x_field_from_fmt() argument
119 if (fmt->fields[f].field_id == field) in tic6x_field_from_fmt()
128 tic6x_field_width (const tic6x_insn_field *field) in tic6x_field_width() argument
133 if (!field->num_bitfields) in tic6x_field_width()
134 return field->bitfields[0].width; in tic6x_field_width()
136 for (i = 0 ; i < field->num_bitfields ; i++) in tic6x_field_width()
137 width += field->bitfields[i].width; in tic6x_field_width()
145 tic6x_field_bits (unsigned int opcode, const tic6x_insn_field *field) in tic6x_field_bits() argument
150 if (!field->num_bitfields) in tic6x_field_bits()
151 return (opcode >> field->bitfields[0].low_pos) & ((1u << field->bitfields[0].width) - 1); in tic6x_field_bits()
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Daarch64-asm.c41 const aarch64_field *field; in insert_fields() local
51 field = &fields[kind]; in insert_fields()
53 value >>= field->width; in insert_fields()
217 aarch64_field field = {0, 0}; in aarch64_ins_ldst_elemlist() local
252 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); in aarch64_ins_ldst_elemlist()
253 insert_field_2 (&field, code, opcodeh2, 0); in aarch64_ins_ldst_elemlist()
360 aarch64_field field = {0, 0}; in aarch64_ins_advsimd_imm_modified() local
391 gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */ in aarch64_ins_advsimd_imm_modified()
393 gen_sub_field (FLD_cmode, 1, 1, &field); /* per halfword */ in aarch64_ins_advsimd_imm_modified()
399 gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ in aarch64_ins_advsimd_imm_modified()
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Dia64-gen.c887 irf_operand (int op, const char *field) in irf_operand() argument
889 if (!field) in irf_operand()
898 return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) in irf_operand()
899 || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) in irf_operand()
900 || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) in irf_operand()
901 || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) in irf_operand()
902 || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) in irf_operand()
903 || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) in irf_operand()
904 || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) in irf_operand()
905 || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid")) in irf_operand()
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Dmep-asm.c73 CGEN_KEYWORD *keyword_table, long *field) in parse_csrn() argument
78 err = cgen_parse_keyword (cd, strp, keyword_table, field); in parse_csrn()
85 *field = value; in parse_csrn()
99 long *field) in parse_ivc2_cr() argument
101 return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); in parse_ivc2_cr()
112 long *field) in parse_ivc2_ccr() argument
114 return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); in parse_ivc2_ccr()
120 CGEN_KEYWORD *keyword_table, long *field) in parse_tpreg() argument
124 err = cgen_parse_keyword (cd, strp, keyword_table, field); in parse_tpreg()
127 if (*field != 13) in parse_tpreg()
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Daarch64-dis.c130 const aarch64_field *field; in extract_fields() local
141 field = &fields[kind]; in extract_fields()
142 value <<= field->width; in extract_fields()
424 aarch64_field field = {0, 0}; in aarch64_ext_ldst_elemlist() local
432 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); in aarch64_ext_ldst_elemlist()
433 opcodeh2 = extract_field_2 (&field, code, 0); in aarch64_ext_ldst_elemlist()
625 aarch64_field field = {0, 0}; in aarch64_ext_advsimd_imm_modified() local
662 case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ in aarch64_ext_advsimd_imm_modified()
663 case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ in aarch64_ext_advsimd_imm_modified()
664 case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ in aarch64_ext_advsimd_imm_modified()
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/toolchain/binutils/binutils-2.27/gas/
Dcgen.c84 struct cgen_maybe_multi_ifield * field; member
257 fixP->fx_cgen.field = NULL; in gas_cgen_record_fixup()
292 fixP->fx_cgen.field = NULL; in gas_cgen_record_fixup_exp()
651 fixP->fx_cgen.field = fixups[i].field; in gas_cgen_finish_insn()
674 const CGEN_MAYBE_MULTI_IFLD * field, in queue_fixup_recursively() argument
678 if (field && field->count) in queue_fixup_recursively()
682 for (i = 0; i < field->count; ++ i) in queue_fixup_recursively()
684 & (field->val.multi[i]), signed_p, i); in queue_fixup_recursively()
692 (field ? field->val.leaf->name : "??")); in queue_fixup_recursively()
695 if (field && part_of_multi != -1) in queue_fixup_recursively()
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/toolchain/binutils/binutils-2.27/include/coff/
Decoff.h249 #define AUX_GET_ANY(bigend, ax, field) \ argument
250 ((bigend) ? bfd_getb32 ((ax)->field) : bfd_getl32 ((ax)->field))
259 #define AUX_PUT_ANY(bigend, val, ax, field) \ argument
261 ? (bfd_putb32 ((bfd_vma) (val), (ax)->field), 0) \
262 : (bfd_putl32 ((bfd_vma) (val), (ax)->field), 0))
DChangeLog-9103235 * intental.h: Add load page field.
419 * internal.h (struct internal_filehdr): Add f_target_id field.
432 F_APCS_SET for the f_flags field of the filehdr structure. Added new
434 information in the flags field of the internal_f structure used by BFD
519 (struct internal_scnhdr): Use SCNNMLEN for s_name field.
600 * internal.h (struct internal_aouthdr): Add o_cputype field.
605 * rs6000.h (AOUTHDR): Add o_maxdata field. Add comments.
608 * internal.h (struct internal_aouthdr): Add o_maxdata field.
649 * internal.h (struct internal_syment): Change n_numaux field from
712 * sym.h (struct pdr): field "prof" added.
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/
Dreloc-bad-3.l33 [^:]*:9: Error: value too large for 2-byte field
34 [^:]*:11: Error: value too large for 2-byte field
35 [^:]*:13: Error: value too large for 1-byte field
36 [^:]*:15: Error: value too large for 1-byte field
/toolchain/binutils/binutils-2.27/include/nlm/
DChangeLog-931539 dataOffset, and dataStamp field.
47 from nlmNAME(external_cygnus_section_header). Change stamp field
48 to 8 bytes. Add bytes field.
50 nlm_internal_cygnus_section_header. Change stamp field to 8
62 debugRecOffset and debugRecLength fields. Add data field.
/toolchain/binutils/binutils-2.27/include/
DChangeLog-910332 * bfdlink.h (struct bfd_link_info): Remove mpc860c0 field.
36 * dis-asm.h (struct disassemble_info): Add new field
41 specific function for the symbol_is_valid field.
43 function pointed to by the symbol_is_valid field.
71 * bfdlink.h (struct bfd_elf_version_expr): Remove match field.
77 (struct bfd_elf_version_tree): Add match field.
83 * floatformat.h (struct floatformat): Add field "is_valid".
293 field pei386_runtime_pseudo_reloc.
345 (struct bfd_link_info): Add new field 'common_skip_ar_symbols'.
384 pei386_auto_import field to int so that -1 can mean enabled by
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