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Searched refs:simm (Results 1 – 6 of 6) sorted by relevance

/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Dldst-reg-unscaled-imm.s35 .macro op2 op, reg, simm argument
36 \op \reg\()7, [sp, #\simm]
41 .irp simm, -256, -171
42 op2 \op\suffix, \reg, \simm
45 .irp simm, 0, 2, 4, 8, 16, 85, 255
46 op2 \op\suffix, \reg, \simm
53 .irp simm, -256, -171
54 op2 \op, \reg, \simm
57 .irp simm, 0, 2, 4, 8, 16, 85, 255
58 op2 \op, \reg, \simm
Dldst-reg-uns-imm.s37 .macro op2 op, reg, simm argument
38 \op \reg\()7, [sp, #\simm]
44 .irp simm, -256, -171
45 op2 \op\suffix, \reg, \simm
48 .irp simm, 0, 2, 4, 8, 16, 85, 255
49 op2 \op\suffix, \reg, \simm
57 .irp simm, -256, -171
58 op2 \op, \reg, \simm
61 .irp simm, 0, 2, 4, 8, 16, 85, 255
62 op2 \op, \reg, \simm
Dldst-reg-imm-pre-ind.s23 .macro op2 op, reg, simm argument
24 \op \reg\()7, [sp, #\simm]!
29 .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
30 op2 \op\suffix, \reg, \simm
37 .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
38 op2 \op, \reg, \simm
/toolchain/binutils/binutils-2.27/cpu/
Dfrv.cpu4015 ; Format: INT, Logic, Shift r-simm
4017 (define-pmacro (int-logic-r-simm name operation op comment)
4030 (int-logic-r-simm addi add OP_10 "add reg/immed")
4031 (int-logic-r-simm subi sub OP_14 "sub reg/immed")
4032 (int-logic-r-simm andi and OP_20 "and reg/immed")
4033 (int-logic-r-simm ori or OP_22 "or reg/immed")
4034 (int-logic-r-simm xori xor OP_24 "xor reg/immed")
4090 (define-pmacro (multiply-r-simm name signop op comment)
4103 (multiply-r-simm smuli ext OP_18 "signed multiply reg/immed")
4104 (multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed")
[all …]
Dor1korbis.cpu876 (define-pmacro (alu-insn-simm mnemonic)
904 (alu-insn-simm xor)
906 (define-pmacro (alu-carry-insn-simm mnemonic)
927 (alu-carry-insn-simm add)
DChangeLog750 (store-double-r-simm): Ditto.