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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/
Davx512cd_vl.s10 vpconflictd (%eax){1to4}, %xmm6{%k7} # AVX512{CD,VL}
15 vpconflictd 508(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} Disp8
16 vpconflictd 512(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL}
17 vpconflictd -512(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} Disp8
18 vpconflictd -516(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL}
49 vpconflictq (%eax){1to4}, %ymm6{%k7} # AVX512{CD,VL}
54 vpconflictq 1016(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} Disp8
55 vpconflictq 1024(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL}
56 vpconflictq -1024(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} Disp8
57 vpconflictq -1032(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL}
[all …]
Dx86-64-avx512cd_vl.s11 vpconflictd (%rcx){1to4}, %xmm30 # AVX512{CD,VL}
16 vpconflictd 508(%rdx){1to4}, %xmm30 # AVX512{CD,VL} Disp8
17 vpconflictd 512(%rdx){1to4}, %xmm30 # AVX512{CD,VL}
18 vpconflictd -512(%rdx){1to4}, %xmm30 # AVX512{CD,VL} Disp8
19 vpconflictd -516(%rdx){1to4}, %xmm30 # AVX512{CD,VL}
53 vpconflictq (%rcx){1to4}, %ymm30 # AVX512{CD,VL}
58 vpconflictq 1016(%rdx){1to4}, %ymm30 # AVX512{CD,VL} Disp8
59 vpconflictq 1024(%rdx){1to4}, %ymm30 # AVX512{CD,VL}
60 vpconflictq -1024(%rdx){1to4}, %ymm30 # AVX512{CD,VL} Disp8
61 vpconflictq -1032(%rdx){1to4}, %ymm30 # AVX512{CD,VL}
[all …]
Davx512dq_vl.s45 vcvtpd2qq (%eax){1to4}, %ymm6{%k7} # AVX512{DQ,VL}
50 vcvtpd2qq 1016(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL} Disp8
51 vcvtpd2qq 1024(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL}
52 vcvtpd2qq -1024(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL} Disp8
53 vcvtpd2qq -1032(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL}
71 vcvtpd2uqq (%eax){1to4}, %ymm6{%k7} # AVX512{DQ,VL}
76 vcvtpd2uqq 1016(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL} Disp8
77 vcvtpd2uqq 1024(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL}
78 vcvtpd2uqq -1024(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL} Disp8
79 vcvtpd2uqq -1032(%edx){1to4}, %ymm6{%k7} # AVX512{DQ,VL}
[all …]
Dx86-64-avx512dq_vl.s50 vcvtpd2qq (%rcx){1to4}, %ymm30 # AVX512{DQ,VL}
55 vcvtpd2qq 1016(%rdx){1to4}, %ymm30 # AVX512{DQ,VL} Disp8
56 vcvtpd2qq 1024(%rdx){1to4}, %ymm30 # AVX512{DQ,VL}
57 vcvtpd2qq -1024(%rdx){1to4}, %ymm30 # AVX512{DQ,VL} Disp8
58 vcvtpd2qq -1032(%rdx){1to4}, %ymm30 # AVX512{DQ,VL}
78 vcvtpd2uqq (%rcx){1to4}, %ymm30 # AVX512{DQ,VL}
83 vcvtpd2uqq 1016(%rdx){1to4}, %ymm30 # AVX512{DQ,VL} Disp8
84 vcvtpd2uqq 1024(%rdx){1to4}, %ymm30 # AVX512{DQ,VL}
85 vcvtpd2uqq -1024(%rdx){1to4}, %ymm30 # AVX512{DQ,VL} Disp8
86 vcvtpd2uqq -1032(%rdx){1to4}, %ymm30 # AVX512{DQ,VL}
[all …]
Dx86-64-avx512dq_vl.d56 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b 31[ ]*vcvtpd2qq \(%rcx\)\{1to4\},%ymm30
61 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b 72 7f[ ]*vcvtpd2qq 0x3f8\(%rdx\)\{1to4\},%ymm30
62 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b b2 00 04 00 00[ ]*vcvtpd2qq 0x400\(%rdx\)\{1to4\},%ymm30
63 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b 72 80[ ]*vcvtpd2qq -0x400\(%rdx\)\{1to4\},%ymm30
64 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b b2 f8 fb ff ff[ ]*vcvtpd2qq -0x408\(%rdx\)\{1to4\},%ymm30
84 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 31[ ]*vcvtpd2uqq \(%rcx\)\{1to4\},%ymm30
89 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 72 7f[ ]*vcvtpd2uqq 0x3f8\(%rdx\)\{1to4\},%ymm30
90 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 b2 00 04 00 00[ ]*vcvtpd2uqq 0x400\(%rdx\)\{1to4\},%ymm30
91 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 72 80[ ]*vcvtpd2uqq -0x400\(%rdx\)\{1to4\},%ymm30
92 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 b2 f8 fb ff ff[ ]*vcvtpd2uqq -0x408\(%rdx\)\{1to4\},%ymm30
[all …]
Dx86-64-avx512cd_vl.d17 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 31[ ]*vpconflictd \(%rcx\)\{1to4\},%xmm30
22 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 72 7f[ ]*vpconflictd 0x1fc\(%rdx\)\{1to4\},%xmm30
23 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 b2 00 02 00 00[ ]*vpconflictd 0x200\(%rdx\)\{1to4\},%xmm30
24 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 72 80[ ]*vpconflictd -0x200\(%rdx\)\{1to4\},%xmm30
25 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 b2 fc fd ff ff[ ]*vpconflictd -0x204\(%rdx\)\{1to4\},%xmm30
59 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 31[ ]*vpconflictq \(%rcx\)\{1to4\},%ymm30
64 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 72 7f[ ]*vpconflictq 0x3f8\(%rdx\)\{1to4\},%ymm30
65 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 b2 00 04 00 00[ ]*vpconflictq 0x400\(%rdx\)\{1to4\},%ymm30
66 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 72 80[ ]*vpconflictq -0x400\(%rdx\)\{1to4\},%ymm30
67 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 b2 f8 fb ff ff[ ]*vpconflictq -0x408\(%rdx\)\{1to4\},%ymm30
[all …]
Dx86-64-avx512f_vl.s25 vaddpd (%rcx){1to4}, %ymm29, %ymm30 # AVX512{F,VL}
30 vaddpd 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{F,VL} Disp8
31 vaddpd 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{F,VL}
32 vaddpd -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{F,VL} Disp8
33 vaddpd -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{F,VL}
39 vaddps (%rcx){1to4}, %xmm29, %xmm30 # AVX512{F,VL}
44 vaddps 508(%rdx){1to4}, %xmm29, %xmm30 # AVX512{F,VL} Disp8
45 vaddps 512(%rdx){1to4}, %xmm29, %xmm30 # AVX512{F,VL}
46 vaddps -512(%rdx){1to4}, %xmm29, %xmm30 # AVX512{F,VL} Disp8
47 vaddps -516(%rdx){1to4}, %xmm29, %xmm30 # AVX512{F,VL}
[all …]
Davx512ifma_vl.s23 vpmadd52luq (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
28 vpmadd52luq 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
29 vpmadd52luq 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
30 vpmadd52luq -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
31 vpmadd52luq -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
49 vpmadd52huq (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
54 vpmadd52huq 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
55 vpmadd52huq 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
56 vpmadd52huq -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
57 vpmadd52huq -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
[all …]
Dx86-64-avx512ifma_vl.s25 vpmadd52luq (%rcx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
30 vpmadd52luq 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
31 vpmadd52luq 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
32 vpmadd52luq -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
33 vpmadd52luq -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
53 vpmadd52huq (%rcx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
58 vpmadd52huq 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
59 vpmadd52huq 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
60 vpmadd52huq -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
61 vpmadd52huq -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
[all …]
Dx86-64-avx512dq_vl-intel.d56 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b 31[ ]*vcvtpd2qq ymm30,QWORD PTR \[rcx\]\{1to4\}
61 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b 72 7f[ ]*vcvtpd2qq ymm30,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
62 …]*[a-f0-9]+:[ ]*62 61 fd 38 7b b2 00 04 00 00[ ]*vcvtpd2qq ymm30,QWORD PTR \[rdx\+0x400\]\{1to4\}
63 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b 72 80[ ]*vcvtpd2qq ymm30,QWORD PTR \[rdx-0x400\]\{1to4\}
64 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 7b b2 f8 fb ff ff[ ]*vcvtpd2qq ymm30,QWORD PTR \[rdx-0x408\]\{1to4…
84 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 31[ ]*vcvtpd2uqq ymm30,QWORD PTR \[rcx\]\{1to4\}
89 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 72 7f[ ]*vcvtpd2uqq ymm30,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
90 …*[a-f0-9]+:[ ]*62 61 fd 38 79 b2 00 04 00 00[ ]*vcvtpd2uqq ymm30,QWORD PTR \[rdx\+0x400\]\{1to4\}
91 [ ]*[a-f0-9]+:[ ]*62 61 fd 38 79 72 80[ ]*vcvtpd2uqq ymm30,QWORD PTR \[rdx-0x400\]\{1to4\}
92 …]*[a-f0-9]+:[ ]*62 61 fd 38 79 b2 f8 fb ff ff[ ]*vcvtpd2uqq ymm30,QWORD PTR \[rdx-0x408\]\{1to4\}
[all …]
Dx86-64-avx512ifma_vl.d31 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to4\},%ymm29,%ymm30
36 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
37 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to4\},%ymm29,%ymm…
38 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
39 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to4\},%ymm29,%ym…
59 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to4\},%ymm29,%ymm30
64 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
65 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to4\},%ymm29,%ymm…
66 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
67 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to4\},%ymm29,%ym…
[all …]
Dx86-64-avx512f_vl.d31 [ ]*[a-f0-9]+:[ ]*62 61 95 30 58 31[ ]*vaddpd \(%rcx\)\{1to4\},%ymm29,%ymm30
36 [ ]*[a-f0-9]+:[ ]*62 61 95 30 58 72 7f[ ]*vaddpd 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
37 [ ]*[a-f0-9]+:[ ]*62 61 95 30 58 b2 00 04 00 00[ ]*vaddpd 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
38 [ ]*[a-f0-9]+:[ ]*62 61 95 30 58 72 80[ ]*vaddpd -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
39 [ ]*[a-f0-9]+:[ ]*62 61 95 30 58 b2 f8 fb ff ff[ ]*vaddpd -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
45 [ ]*[a-f0-9]+:[ ]*62 61 14 10 58 31[ ]*vaddps \(%rcx\)\{1to4\},%xmm29,%xmm30
50 [ ]*[a-f0-9]+:[ ]*62 61 14 10 58 72 7f[ ]*vaddps 0x1fc\(%rdx\)\{1to4\},%xmm29,%xmm30
51 [ ]*[a-f0-9]+:[ ]*62 61 14 10 58 b2 00 02 00 00[ ]*vaddps 0x200\(%rdx\)\{1to4\},%xmm29,%xmm30
52 [ ]*[a-f0-9]+:[ ]*62 61 14 10 58 72 80[ ]*vaddps -0x200\(%rdx\)\{1to4\},%xmm29,%xmm30
53 [ ]*[a-f0-9]+:[ ]*62 61 14 10 58 b2 fc fd ff ff[ ]*vaddps -0x204\(%rdx\)\{1to4\},%xmm29,%xmm30
[all …]
Davx512cd_vl.d16 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 30[ ]*vpconflictd \(%eax\)\{1to4\},%xmm6\{%k7\}
21 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 72 7f[ ]*vpconflictd 0x1fc\(%edx\)\{1to4\},%xmm6\{%k7\}
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 b2 00 02 00 00[ ]*vpconflictd 0x200\(%edx\)\{1to4\},%xmm6\{%k7\}
23 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 72 80[ ]*vpconflictd -0x200\(%edx\)\{1to4\},%xmm6\{%k7\}
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 b2 fc fd ff ff[ ]*vpconflictd -0x204\(%edx\)\{1to4\},%xmm6\{%k7…
55 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 30[ ]*vpconflictq \(%eax\)\{1to4\},%ymm6\{%k7\}
60 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 72 7f[ ]*vpconflictq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\}
61 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 b2 00 04 00 00[ ]*vpconflictq 0x400\(%edx\)\{1to4\},%ymm6\{%k7\}
62 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 72 80[ ]*vpconflictq -0x400\(%edx\)\{1to4\},%ymm6\{%k7\}
63 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 b2 f8 fb ff ff[ ]*vpconflictq -0x408\(%edx\)\{1to4\},%ymm6\{%k7…
[all …]
Dx86-64-avx512cd_vl-intel.d17 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 31[ ]*vpconflictd xmm30,DWORD PTR \[rcx\]\{1to4\}
22 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 72 7f[ ]*vpconflictd xmm30,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
23 …[a-f0-9]+:[ ]*62 62 7d 18 c4 b2 00 02 00 00[ ]*vpconflictd xmm30,DWORD PTR \[rdx\+0x200\]\{1to4\}
24 [ ]*[a-f0-9]+:[ ]*62 62 7d 18 c4 72 80[ ]*vpconflictd xmm30,DWORD PTR \[rdx-0x200\]\{1to4\}
25 …*[a-f0-9]+:[ ]*62 62 7d 18 c4 b2 fc fd ff ff[ ]*vpconflictd xmm30,DWORD PTR \[rdx-0x204\]\{1to4\}
59 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 31[ ]*vpconflictq ymm30,QWORD PTR \[rcx\]\{1to4\}
64 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 72 7f[ ]*vpconflictq ymm30,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
65 …[a-f0-9]+:[ ]*62 62 fd 38 c4 b2 00 04 00 00[ ]*vpconflictq ymm30,QWORD PTR \[rdx\+0x400\]\{1to4\}
66 [ ]*[a-f0-9]+:[ ]*62 62 fd 38 c4 72 80[ ]*vpconflictq ymm30,QWORD PTR \[rdx-0x400\]\{1to4\}
67 …*[a-f0-9]+:[ ]*62 62 fd 38 c4 b2 f8 fb ff ff[ ]*vpconflictq ymm30,QWORD PTR \[rdx-0x408\]\{1to4\}
[all …]
Davx512dq_vl.d51 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b 30[ ]*vcvtpd2qq \(%eax\)\{1to4\},%ymm6\{%k7\}
56 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b 72 7f[ ]*vcvtpd2qq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\}
57 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b b2 00 04 00 00[ ]*vcvtpd2qq 0x400\(%edx\)\{1to4\},%ymm6\{%k7\}
58 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b 72 80[ ]*vcvtpd2qq -0x400\(%edx\)\{1to4\},%ymm6\{%k7\}
59 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b b2 f8 fb ff ff[ ]*vcvtpd2qq -0x408\(%edx\)\{1to4\},%ymm6\{%k7\}
77 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 30[ ]*vcvtpd2uqq \(%eax\)\{1to4\},%ymm6\{%k7\}
82 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 72 7f[ ]*vcvtpd2uqq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\}
83 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 b2 00 04 00 00[ ]*vcvtpd2uqq 0x400\(%edx\)\{1to4\},%ymm6\{%k7\}
84 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 72 80[ ]*vcvtpd2uqq -0x400\(%edx\)\{1to4\},%ymm6\{%k7\}
85 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 b2 f8 fb ff ff[ ]*vcvtpd2uqq -0x408\(%edx\)\{1to4\},%ymm6\{%k7\}
[all …]
Dx86-64-avx512ifma_vl-intel.d31 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 31[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
36 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 7f[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4…
37 …9]+:[ ]*62 62 95 30 b4 b2 00 04 00 00[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
38 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 80[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
39 …-9]+:[ ]*62 62 95 30 b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
59 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 31[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
64 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 7f[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4…
65 …9]+:[ ]*62 62 95 30 b5 b2 00 04 00 00[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
66 [ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 80[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
67 …-9]+:[ ]*62 62 95 30 b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
[all …]
Davx512dq_vl-intel.d51 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b 30[ ]*vcvtpd2qq ymm6\{k7\},QWORD PTR \[eax\]\{1to4\}
56 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b 72 7f[ ]*vcvtpd2qq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\}
57 …f0-9]+:[ ]*62 f1 fd 3f 7b b2 00 04 00 00[ ]*vcvtpd2qq ymm6\{k7\},QWORD PTR \[edx\+0x400\]\{1to4\}
58 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 7b 72 80[ ]*vcvtpd2qq ymm6\{k7\},QWORD PTR \[edx-0x400\]\{1to4\}
59 …-f0-9]+:[ ]*62 f1 fd 3f 7b b2 f8 fb ff ff[ ]*vcvtpd2qq ymm6\{k7\},QWORD PTR \[edx-0x408\]\{1to4\}
77 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 30[ ]*vcvtpd2uqq ymm6\{k7\},QWORD PTR \[eax\]\{1to4\}
82 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 72 7f[ ]*vcvtpd2uqq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\}
83 …0-9]+:[ ]*62 f1 fd 3f 79 b2 00 04 00 00[ ]*vcvtpd2uqq ymm6\{k7\},QWORD PTR \[edx\+0x400\]\{1to4\}
84 [ ]*[a-f0-9]+:[ ]*62 f1 fd 3f 79 72 80[ ]*vcvtpd2uqq ymm6\{k7\},QWORD PTR \[edx-0x400\]\{1to4\}
85 …f0-9]+:[ ]*62 f1 fd 3f 79 b2 f8 fb ff ff[ ]*vcvtpd2uqq ymm6\{k7\},QWORD PTR \[edx-0x408\]\{1to4\}
[all …]
Davx512cd_vl-intel.d16 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 30[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[eax\]\{1to4\}
21 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 72 7f[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to4\}
22 …-9]+:[ ]*62 f2 7d 1f c4 b2 00 02 00 00[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[edx\+0x200\]\{1to4\}
23 [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f c4 72 80[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[edx-0x200\]\{1to4\}
24 …0-9]+:[ ]*62 f2 7d 1f c4 b2 fc fd ff ff[ ]*vpconflictd xmm6\{k7\},DWORD PTR \[edx-0x204\]\{1to4\}
55 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 30[ ]*vpconflictq ymm6\{k7\},QWORD PTR \[eax\]\{1to4\}
60 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 72 7f[ ]*vpconflictq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\}
61 …-9]+:[ ]*62 f2 fd 3f c4 b2 00 04 00 00[ ]*vpconflictq ymm6\{k7\},QWORD PTR \[edx\+0x400\]\{1to4\}
62 [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f c4 72 80[ ]*vpconflictq ymm6\{k7\},QWORD PTR \[edx-0x400\]\{1to4\}
63 …0-9]+:[ ]*62 f2 fd 3f c4 b2 f8 fb ff ff[ ]*vpconflictq ymm6\{k7\},QWORD PTR \[edx-0x408\]\{1to4\}
[all …]
Davx512ifma_vl.d29 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 30[ ]*vpmadd52luq \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
34 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
35 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to4\},%ymm5,%ymm6…
36 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
37 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to4\},%ymm5,%ymm…
55 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 30[ ]*vpmadd52huq \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
60 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
61 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to4\},%ymm5,%ymm6…
62 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
63 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to4\},%ymm5,%ymm…
[all …]
Davx512ifma_vl-intel.d29 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 30[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
34 …a-f0-9]+:[ ]*62 f2 d5 3f b4 72 7f[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
35 …[ ]*62 f2 d5 3f b4 b2 00 04 00 00[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
36 …[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 80[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
37 …:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
55 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 30[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
60 …a-f0-9]+:[ ]*62 f2 d5 3f b5 72 7f[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
61 …[ ]*62 f2 d5 3f b5 b2 00 04 00 00[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
62 …[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 80[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
63 …:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
[all …]
Davx512vbmi_vl.s71 vpmultishiftqb (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
76 vpmultishiftqb 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
77 vpmultishiftqb 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
78 vpmultishiftqb -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL} Disp8
79 vpmultishiftqb -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{VBMI,VL}
147 vpmultishiftqb ymm6{k7}, ymm5, [eax]{1to4} # AVX512{VBMI,VL}
152 vpmultishiftqb ymm6{k7}, ymm5, [edx+1016]{1to4} # AVX512{VBMI,VL} Disp8
153 vpmultishiftqb ymm6{k7}, ymm5, [edx+1024]{1to4} # AVX512{VBMI,VL}
154 vpmultishiftqb ymm6{k7}, ymm5, [edx-1024]{1to4} # AVX512{VBMI,VL} Disp8
155 vpmultishiftqb ymm6{k7}, ymm5, [edx-1032]{1to4} # AVX512{VBMI,VL}
Dx86-64-avx512vbmi_vl.s79 vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL}
84 vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
85 vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL}
86 vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL} Disp8
87 vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{VBMI,VL}
163 vpmultishiftqb ymm30, ymm29, [rcx]{1to4} # AVX512{VBMI,VL}
168 vpmultishiftqb ymm30, ymm29, [rdx+1016]{1to4} # AVX512{VBMI,VL} Disp8
169 vpmultishiftqb ymm30, ymm29, [rdx+1024]{1to4} # AVX512{VBMI,VL}
170 vpmultishiftqb ymm30, ymm29, [rdx-1024]{1to4} # AVX512{VBMI,VL} Disp8
171 vpmultishiftqb ymm30, ymm29, [rdx-1032]{1to4} # AVX512{VBMI,VL}
Dx86-64-avx512vbmi_vl.d85 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to4\},%ymm29,%ymm30
90 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
91 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to4\},%ymm29,%…
92 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
93 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to4\},%ymm29,…
167 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb \(%rcx\)\{1to4\},%ymm29,%ymm30
172 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
173 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb 0x400\(%rdx\)\{1to4\},%ymm29,%…
174 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
175 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb -0x408\(%rdx\)\{1to4\},%ymm29,…
Dx86-64-avx512vbmi_vl-intel.d85 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
90 …[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
91 …:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
92 …*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
93 …+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
167 [ ]*[a-f0-9]+:[ ]*62 62 95 30 83 31[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
172 …[a-f0-9]+:[ ]*62 62 95 30 83 72 7f[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
173 …:[ ]*62 62 95 30 83 b2 00 04 00 00[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
174 …*[a-f0-9]+:[ ]*62 62 95 30 83 72 80[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
175 …+:[ ]*62 62 95 30 83 b2 f8 fb ff ff[ ]*vpmultishiftqb ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-sh/sh64/
Drelfail.s15 .global to4 symbol
16 to4: label

12