| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| D | rdma-directive.d | 11 0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
12 4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
13 8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
14 c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
15 10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
16 14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
17 18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
18 1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
23 30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
24 34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
[all …]
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| D | rdma.d | 10 0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
11 4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
12 8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
13 c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
14 10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
15 14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
16 18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
17 1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
22 30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
23 34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
[all …]
|
| D | illegal.l | 54 [^:]*:86: Error: .*`ext v0.16b,v1.16b,v2.16b,20'
58 [^:]*:93: Error: .*`fmov v2.S\[2\],x0'
60 [^:]*:95: Error: .*`fmov v2.D\[1\],w0'
66 [^:]*:103: Error: .*`st1 {v2.s,v3.s}\[1\],\[x4\]'
68 [^:]*:105: Error: .*`st2 {v2.s,v2.s,v3.s}\[1\],\[x4\]'
70 [^:]*:107: Error: .*`st3 {v2.s,v3.s,v4.s,v5.s}\[1\],\[x4\]'
72 [^:]*:109: Error: .*`st4 {v2.s}\[1\],\[x4\]'
74 [^:]*:112: Error: .*`st2 {v2.b,v4.b}\[1\],\[x4\]'
76 [^:]*:114: Error: .*`st3 {v2.b,v4.b,v6.b}\[1\],\[x4\]'
78 [^:]*:116: Error: .*`st4 {v2.b,v4.b,v6.b,v8.b}\[1\],\[x4\]'
[all …]
|
| D | advsimd-fp16.d | 9 [0-9a-f]+: 4e63c441 fmaxnm v1.2d, v2.2d, v3.2d
10 [0-9a-f]+: 0e23c441 fmaxnm v1.2s, v2.2s, v3.2s
11 [0-9a-f]+: 4e23c441 fmaxnm v1.4s, v2.4s, v3.4s
13 [0-9a-f]+: 0e430441 fmaxnm v1.4h, v2.4h, v3.4h
15 [0-9a-f]+: 4e430441 fmaxnm v1.8h, v2.8h, v3.8h
16 [0-9a-f]+: 6e63c441 fmaxnmp v1.2d, v2.2d, v3.2d
17 [0-9a-f]+: 2e23c441 fmaxnmp v1.2s, v2.2s, v3.2s
18 [0-9a-f]+: 6e23c441 fmaxnmp v1.4s, v2.4s, v3.4s
20 [0-9a-f]+: 2e430441 fmaxnmp v1.4h, v2.4h, v3.4h
22 [0-9a-f]+: 6e430441 fmaxnmp v1.8h, v2.8h, v3.8h
[all …]
|
| D | neon-vfp-reglist-post.d | 10 8: 0cdf6000 ld1 {v0.8b-v2.8b}, \[x0\], #24
14 18: 0cdf6400 ld1 {v0.4h-v2.4h}, \[x0\], #24
18 28: 0cdf6800 ld1 {v0.2s-v2.2s}, \[x0\], #24
22 38: 0cdf6c00 ld1 {v0.1d-v2.1d}, \[x0\], #24
26 48: 0c9f6000 st1 {v0.8b-v2.8b}, \[x0\], #24
30 58: 0c9f6400 st1 {v0.4h-v2.4h}, \[x0\], #24
34 68: 0c9f6800 st1 {v0.2s-v2.2s}, \[x0\], #24
38 78: 0c9f6c00 st1 {v0.1d-v2.1d}, \[x0\], #24
42 88: 4cdf6000 ld1 {v0.16b-v2.16b}, \[x0\], #48
46 98: 4cdf6400 ld1 {v0.8h-v2.8h}, \[x0\], #48
[all …]
|
| D | neon-vfp-reglist.d | 10 8: 0c406000 ld1 {v0.8b-v2.8b}, \[x0\]
13 14: 0c404000 ld3 {v0.8b-v2.8b}, \[x0\]
17 24: 0c006000 st1 {v0.8b-v2.8b}, \[x0\]
20 30: 0c004000 st3 {v0.8b-v2.8b}, \[x0\]
24 40: 4c406000 ld1 {v0.16b-v2.16b}, \[x0\]
27 4c: 4c404000 ld3 {v0.16b-v2.16b}, \[x0\]
31 5c: 4c006000 st1 {v0.16b-v2.16b}, \[x0\]
34 68: 4c004000 st3 {v0.16b-v2.16b}, \[x0\]
38 78: 0c406400 ld1 {v0.4h-v2.4h}, \[x0\]
41 84: 0c404400 ld3 {v0.4h-v2.4h}, \[x0\]
[all …]
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| D | illegal.s | 51 aese v1.8b, v2.8b
59 sha1su0 v0.2d, v1.2d, v2.2d
85 ext v0.8b, v1.8b, v2.8b, 8
86 ext v0.16b, v1.16b, v2.16b, 20
93 fmov v2.S[2], x0
94 fmov v2.S[1], x0
95 fmov v2.D[1], w0
102 ld1 {v1.s, v2.s}[1], [x3]
103 st1 {v2.s, v3.s}[1], [x4]
104 ld2 {v1.s, v2.s, v3.s}[1], [x3]
[all …]
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| D | alias.d | 58 c8: 0ea21c20 orr v0.8b, v1.8b, v2.8b
75 10c: 0f08a448 sxtl v8.8h, v2.8b
76 110: 0f08a448 sxtl v8.8h, v2.8b
77 114: 4f08a448 sxtl2 v8.8h, v2.16b
78 118: 4f08a448 sxtl2 v8.8h, v2.16b
79 11c: 0f10a448 sxtl v8.4s, v2.4h
80 120: 0f10a448 sxtl v8.4s, v2.4h
81 124: 4f10a448 sxtl2 v8.4s, v2.8h
82 128: 4f10a448 sxtl2 v8.4s, v2.8h
83 12c: 0f20a448 sxtl v8.2d, v2.2s
[all …]
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| D | no-aliases.d | 59 c8: 0ea21c20 orr v0.8b, v1.8b, v2.8b
76 10c: 0f08a448 sshll v8.8h, v2.8b, #0
77 110: 0f08a448 sshll v8.8h, v2.8b, #0
78 114: 4f08a448 sshll2 v8.8h, v2.16b, #0
79 118: 4f08a448 sshll2 v8.8h, v2.16b, #0
80 11c: 0f10a448 sshll v8.4s, v2.4h, #0
81 120: 0f10a448 sshll v8.4s, v2.4h, #0
82 124: 4f10a448 sshll2 v8.4s, v2.8h, #0
83 128: 4f10a448 sshll2 v8.4s, v2.8h, #0
84 12c: 0f20a448 sshll v8.2d, v2.2s, #0
[all …]
|
| D | advsimd-fp16.s | 7 \op v1.2d, v2.2d, v3.2d
8 \op v1.2s, v2.2s, v3.2s
9 \op v1.4s, v2.4s, v3.4s
11 \op v1.4h, v2.4h, v3.4h
13 \op v1.8h, v2.8h, v3.8h
161 \op v1.2d, v2.2d, v3.d[1]
162 \op v1.2s, v2.2s, v3.s[2]
163 \op v1.4s, v2.4s, v3.s[1]
165 \op v1.4h, v2.4h, v3.h[0]
167 \op v1.8h, v2.8h, v3.h[0]
[all …]
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| D | neon-vfp-reglist-post.s | 12 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
13 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
25 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
26 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
38 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
39 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
75 \inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #24
76 \inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
77 \inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
78 \inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
[all …]
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| D | alias.s | 80 orr v0.8b, v1.8b, v2.8b
104 \s\()xtl v8.8h, v2.8b
105 \s\()shll v8.8h, v2.8b, #0
106 \s\()xtl2 v8.8h, v2.16b
107 \s\()shll2 v8.8h, v2.16b, #0
108 \s\()xtl v8.4s, v2.4h
109 \s\()shll v8.4s, v2.4h, #0
110 \s\()xtl2 v8.4s, v2.8h
111 \s\()shll2 v8.4s, v2.8h, #0
112 \s\()xtl v8.2d, v2.2s
[all …]
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| D | verbose-error.s | 10 ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
12 add v0.4s, v1.4s, v2.2s
20 ursqrte v2.8b, v3.8b
46 fcvtl2 v1.2d, v2.2d
52 sha1su0 v1.16b, v2.16b, v3.16b
54 shadd v1.2d, v2.2d, v3.2d
56 sqdmulh v1.16b, v2.16b, v3.16b
58 sqdmlal2 v1.16b, v2.16b, v3.16b
|
| D | verbose-error.l | 12 …ers in the list; only 1 register is expected at operand 1 -- `ld1r \{v1.4s,v2.4s,v3.4s\},\[x3\],x4'
14 [^:]*:12: Error: operand mismatch -- `add v0.4s,v1.4s,v2.2s'
56 [^:]*:20: Error: operand mismatch -- `ursqrte v2.8b,v3.8b'
131 [^:]*:46: Info: fcvtl2 v1.2d,v2.4s
133 [^:]*:46: Info: fcvtl2 v1.4s,v2.8h
153 [^:]*:52: Error: operand mismatch -- `sha1su0 v1.16b,v2.16b,v3.16b'
158 [^:]*:54: Info: shadd v1.8b,v2.8b,v3.8b
160 [^:]*:54: Info: shadd v1.16b,v2.16b,v3.16b
161 [^:]*:54: Info: shadd v1.4h,v2.4h,v3.4h
162 [^:]*:54: Info: shadd v1.8h,v2.8h,v3.8h
[all …]
|
| D | diagnostic.s | 11 ext v0.8b, v1.8b, v2.8b, 8
12 ext v0.16b, v1.16b, v2.16b, 20
32 st2 {v0.4s, v1.4s, v2.4s, v3.4s}, [sp], #64
39 shll v1.4s, v2.4h, #15
40 shll v1.4s, v2.4h, #32
41 shl v1.2s, v2.2s, 32
42 sqshrn2 v2.16b, v3.8h, #17
49 movi v2.2s, 255, msl #0
50 movi v2.2s, 255, msl #15
57 cmgt v0.4s, v2.4s, #1
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/all/ |
| D | altmacro.s | 1 .macro m1 v1, v2 argument
5 label&v2:
6 l2: .byte v2
9 .macro m2 v1, v2 argument
10 m1 %(v1), %(v2-v1)
|
| /toolchain/binutils/binutils-2.27/gold/testsuite/ |
| D | large.c | 28 int v2 = 1; variable
39 assert (v2 == 1); in main()
48 assert (&v2 < v3 && &v2 < v4 && &v2 < v5); in main()
|
| D | weak_undef_file1.cc | 49 extern int v2 __attribute__ ((weak));
51 int *v3 = &v2;
65 return (&v2 == NULL) ? -1 : v2; in t2()
|
| D | weak_undef_file2.cc | 44 extern int v2 __attribute__ ((weak));
46 int *v3 = &v2;
60 return (&v2 == NULL) ? -1 : v2; in t2()
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-aarch64/ |
| D | emit-relocs-536.s | 2 .global v2 symbol
3 .size v2, 16384
8 v2: label
14 ldrsw x22, [x14, #:dtprel_lo12_nc:v2]
|
| D | emit-relocs-532.s | 2 .global v2 symbol
3 .size v2, 4100
8 v2: label
14 ldrsb x29, [x4, #:dtprel_lo12_nc:v2]
|
| D | emit-relocs-534.s | 2 .global v2 symbol
3 .size v2, 5000
8 v2: label
14 ldrsh x22, [x14, #:dtprel_lo12_nc:v2]
|
| D | emit-relocs-538.s | 2 .global v2 symbol
3 .size v2, 32768
9 v2: label
16 ldr x2, [x4, #:dtprel_lo12_nc:v2]
|
| D | emit-relocs-88-overflow.s | 2 .global v2 symbol
6 v2: label
10 movk x21, #:dtprel_g0:v2
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| D | vr5400-ill.s | 14 add.ob $v2,$f4,$f6
17 add.ob $v2,$v4,$v6
20 add.ob $v2,$f4,$f6[1]
23 add.ob $v2,$v4,$v6[1]
|