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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Dillegal.l46 [^:]*:77: Error: .*`st2 {v4.2d,v5.2d},\[x3,#3\]'
48 [^:]*:79: Error: .*`st1 {v4.2d,v6.2d,v8.2d},\[x3\]'
50 [^:]*:81: Error: .*`st4 {v4.2d,v6.2d},\[x3\]'
52 [^:]*:83: Error: .*`st2 {v4.2d,v6.2d,v8.2d,v10.2d},\[x3\],48'
70 [^:]*:107: Error: .*`st3 {v2.s,v3.s,v4.s,v5.s}\[1\],\[x4\]'
74 [^:]*:112: Error: .*`st2 {v2.b,v4.b}\[1\],\[x4\]'
76 [^:]*:114: Error: .*`st3 {v2.b,v4.b,v6.b}\[1\],\[x4\]'
78 [^:]*:116: Error: .*`st4 {v2.b,v4.b,v6.b,v8.b}\[1\],\[x4\]'
88 [^:]*:129: Error: .*`ld3r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],x4'
94 [^:]*:136: Error: .*`ld4r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],#32'
[all …]
Dillegal.s77 st2 {v4.2d, v5.2d}, [x3, #3]
78 st2 {v4.2d, v5.2d, v6.2d}, [x3]
79 st1 {v4.2d, v6.2d, v8.2d}, [x3]
80 st3 {v4.2d, v6.2d}, [x3]
81 st4 {v4.2d, v6.2d}, [x3]
82 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3]
83 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48
106 ld3 {v1.s, v2.s, v3.s, v4.s}[1], [x3]
107 st3 {v2.s, v3.s, v4.s, v5.s}[1], [x4]
112 st2 {v2.b, v4.b}[1], [x4]
[all …]
Dneon-ins.d14 18: 4e011c84 mov v4.b\[0\], w4
15 1c: 4e011c84 mov v4.b\[0\], w4
74 108: 4e031c84 mov v4.b\[1\], w4
75 10c: 4e031c84 mov v4.b\[1\], w4
134 1f8: 4e051c84 mov v4.b\[2\], w4
135 1fc: 4e051c84 mov v4.b\[2\], w4
194 2e8: 4e071c84 mov v4.b\[3\], w4
195 2ec: 4e071c84 mov v4.b\[3\], w4
254 3d8: 4e091c84 mov v4.b\[4\], w4
255 3dc: 4e091c84 mov v4.b\[4\], w4
[all …]
Dneon-not.d20 30: 2e205884 mvn v4.8b, v4.8b
21 34: 2e205884 mvn v4.8b, v4.8b
22 38: 6e205884 mvn v4.16b, v4.16b
23 3c: 6e205884 mvn v4.16b, v4.16b
Dverbose-error.l10 [^:]*:8: Error: invalid addressing mode at operand 2 -- `st2 {v4.2d,v5.2d},\[x3,#3\]'
63 [^:]*:22: Info: rev32 v4.8b,v5.8b
65 [^:]*:22: Info: rev32 v4.16b,v5.16b
66 [^:]*:22: Info: rev32 v4.4h,v5.4h
67 [^:]*:22: Info: rev32 v4.8h,v5.8h
Dfp-const0-parse.s41 fcmlt v4.4s, v26.4s, #0
60 fcmlt v4.4s, v26.4s, #0.0
Dfp-const0-parse.d22 38: 4ea0eb44 fcmlt v4.4s, v26.4s, #0.0
37 74: 4ea0eb44 fcmlt v4.4s, v26.4s, #0.0
Dverbose-error.s8 st2 {v4.2d,v5.2d},[x3,#3]
22 rev32 v4.2s, v5.2s
/toolchain/binutils/binutils-2.27/gold/testsuite/
Dlarge.c30 int v4[0x10000] = { 1 }; variable
41 assert (v4[0] == 1 && v4[0xffff] == 0); in main()
47 assert (&v1 < v3 && &v1 < v4 && &v1 < v5); in main()
48 assert (&v2 < v3 && &v2 < v4 && &v2 < v5); in main()
49 assert (&v6 < v3 && &v6 < v4 && &v6 < v5); in main()
50 assert (&v7 < v3 && &v7 < v4 && &v7 < v5); in main()
54 assert (v3 < v4); in main()
56 assert (v5 < v4); in main()
Dtls_test.cc72 static __thread int v4 = 4; variable
111 CHECK_EQ_OR_RETURN(v4, 4); in t4()
112 v4 = 40; in t4()
213 CHECK_EQ_OR_RETURN(v4, 40); in t_last()
Dtwo_file_test_1_v1.cc89 return v4[5] == ','; in t4()
122 char* p8 = &v4[6];
Dtwo_file_test_1.cc84 return v4[5] == ','; in t4()
117 char* p8 = &v4[6];
Ddwp_test_1.cc56 return v4[5] == ','; in testcase4()
89 char* p8 = &v4[6];
Dtwo_file_test_2.cc53 char v4[] = "Hello, world"; variable
Dtwo_file_test_2_v1.cc58 char v4[] = "World, hello"; variable
Ddwp_test_2.cc52 char v4[] = "Hello, world"; variable
Dtwo_file_test_2_tls.cc55 char v4[] = "Hello, world"; variable
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
Dvr5400-ill.s15 add.ob $f2,$v4,$f6
17 add.ob $v2,$v4,$v6
21 add.ob $f2,$v4,$f6[1]
23 add.ob $v2,$v4,$v6[1]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/
Daltivec.d47 94: (10 e5 23 40|40 23 e5 10) vaddshs v7,v5,v4
51 a4: (10 44 30 40|40 30 44 10) vadduhm v2,v4,v6
54 b0: (12 ed 22 80|80 22 ed 12) vadduws v23,v13,v4
57 bc: (10 86 8d 02|02 8d 86 10) vavgsb v4,v6,v17
94 150: (10 99 7b ca|ca 7b 99 10) vctsxs v4,v15,25
112 198: (10 64 0b 82|82 0b 64 10) vminsw v3,v4,v1
126 1d0: (10 24 3e 68|68 3e 24 10) vmsumshm v1,v4,v7,v25
136 1f8: (10 85 41 48|48 41 85 10) vmulosh v4,v5,v8
138 200: (13 a5 20 48|48 20 a5 13) vmulouh v29,v5,v4
149 22c: (10 98 51 4e|4e 51 98 10) vpkswus v4,v24,v10
[all …]
Daltivec2.d59 c4: (12 b2 24 43|43 24 b2 12) vabsduh v21,v18,v4
65 dc: (13 a6 01 3f|3f 01 a6 13) vsubecuq v29,v6,v0,v4
69 ec: (13 d9 20 c2|c2 20 d9 13) vmaxud v30,v25,v4
85 12c: (11 04 26 41|41 26 04 11) bcdsub\. v8,v4,v4,1
101 16c: (13 c4 e5 4e|4e e5 c4 13) vpksdus v30,v4,v28
102 170: (10 04 75 84|84 75 04 10) vnand v0,v4,v14
Dvsx3.d98 .*: (fc 80 58 4a|4a 58 80 fc) xsrqpxp 0,v4,v11,0
102 .*: (fc 53 23 08|08 23 53 fc) xsmaddqp v2,v19,v4
110 .*: (fe 7b 24 08|08 24 7b fe) xssubqp v19,v27,v4
114 .*: (ff 8e 25 08|08 25 8e ff) xscmpuqp cr7,v14,v4
127 .*: (fe f1 26 88|88 26 f1 fe) xscvqpudz v23,v4
131 .*: (fd b9 26 88|88 26 b9 fd) xscvqpsdz v13,v4
Dpower8.d52 a8: (13 02 39 3c|3c 39 02 13) vaddeuqm v24,v2,v7,v4
61 cc: (10 93 58 c7|c7 58 93 10) vcmpequd v4,v19,v11
64 d8: (13 9b 21 88|88 21 9b 13) vmulosw v28,v27,v4
65 dc: (10 64 21 c2|c2 21 64 10) vmaxsd v3,v4,v4
74 100: (10 83 64 08|08 64 83 10) vpmsumb v4,v3,v12
87 134: (10 91 fd 48|48 fd 91 10) vncipher v4,v17,v31
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/m68hc11/
D9s12x-mov.s11 v4=0x89
25 movb #v4, a1,sp
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-arm/
Dattr-merge-arch-2b.s1 .eabi_attribute 6, 0 @Tag_CPU_arch, 0 means pre-v4.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dattr-march-armv4xm.d11 Tag_CPU_arch: v4

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