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/toolchain/binutils/binutils-2.27/opcodes/
Dsparc-opc.c48 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ macro
221 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, 0, v6 },
222 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
223 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, 0, v6 },
224 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, 0, v6 },
225 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },
226 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ld [rs1+0],d */
227 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, 0, v6 },
228 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
229 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, 0, v6 },
[all …]
/toolchain/binutils/binutils-2.27/gold/testsuite/
Dlarge.c32 int v6; variable
43 assert (v6 == 0); in main()
49 assert (&v6 < v3 && &v6 < v4 && &v6 < v5); in main()
Dtls_test.cc74 static __thread int v6; variable
142 return &v6; in f6a()
154 CHECK_EQ_OR_RETURN(v6, 60); in t6()
215 CHECK_EQ_OR_RETURN(v6, 60); in t_last()
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Dillegal.l48 [^:]*:79: Error: .*`st1 {v4.2d,v6.2d,v8.2d},\[x3\]'
50 [^:]*:81: Error: .*`st4 {v4.2d,v6.2d},\[x3\]'
52 [^:]*:83: Error: .*`st2 {v4.2d,v6.2d,v8.2d,v10.2d},\[x3\],48'
76 [^:]*:114: Error: .*`st3 {v2.b,v4.b,v6.b}\[1\],\[x4\]'
78 [^:]*:116: Error: .*`st4 {v2.b,v4.b,v6.b,v8.b}\[1\],\[x4\]'
292 [^:]*:322: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
298 [^:]*:322: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
304 [^:]*:337: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
310 [^:]*:337: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
316 [^:]*:352: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
[all …]
Dneon-ins.d18 28: 4e011cc6 mov v6.b\[0\], w6
19 2c: 4e011cc6 mov v6.b\[0\], w6
78 118: 4e031cc6 mov v6.b\[1\], w6
79 11c: 4e031cc6 mov v6.b\[1\], w6
138 208: 4e051cc6 mov v6.b\[2\], w6
139 20c: 4e051cc6 mov v6.b\[2\], w6
198 2f8: 4e071cc6 mov v6.b\[3\], w6
199 2fc: 4e071cc6 mov v6.b\[3\], w6
258 3e8: 4e091cc6 mov v6.b\[4\], w6
259 3ec: 4e091cc6 mov v6.b\[4\], w6
[all …]
Dillegal.s78 st2 {v4.2d, v5.2d, v6.2d}, [x3]
79 st1 {v4.2d, v6.2d, v8.2d}, [x3]
80 st3 {v4.2d, v6.2d}, [x3]
81 st4 {v4.2d, v6.2d}, [x3]
82 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3]
83 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48
114 st3 {v2.b, v4.b, v6.b}[1], [x4]
116 st4 {v2.b, v4.b, v6.b, v8.b}[1], [x4]
274 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #32
276 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
[all …]
Dneon-not.d28 50: 2e2058c6 mvn v6.8b, v6.8b
29 54: 2e2058c6 mvn v6.8b, v6.8b
30 58: 6e2058c6 mvn v6.16b, v6.16b
31 5c: 6e2058c6 mvn v6.16b, v6.16b
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
Dvr5400-ill.s16 add.ob $f2,$f4,$v6
17 add.ob $v2,$v4,$v6
22 add.ob $f2,$f4,$v6[1]
23 add.ob $v2,$v4,$v6[1]
Dvr5400-ill.l8 .*:16: Error: invalid operands `add.ob \$f2,\$f4,\$v6'
12 .*:22: Error: invalid operands `add.ob \$f2,\$f4,\$v6\[1\]'
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/
Daltivec.d22 30: (7c c0 c8 0c|0c c8 c0 7c) lvsl v6,0,r25
50 a0: (10 c1 ca 00|00 ca c1 10) vaddubs v6,v1,v25
51 a4: (10 44 30 40|40 30 44 10) vadduhm v2,v4,v6
57 bc: (10 86 8d 02|02 8d 86 10) vavgsb v4,v6,v17
60 c8: (10 c7 cc 02|02 cc c7 10) vavgub v6,v7,v25
81 11c: (12 16 33 06|06 33 16 12) vcmpgtsb v16,v22,v6
91 144: (12 3b 32 86|86 32 3b 12) vcmpgtuw v17,v27,v6
96 158: (10 c0 33 0a|0a 33 c0 10) vcfux v6,v6,0
110 190: (12 86 53 02|02 53 86 12) vminsb v20,v6,v10
114 1a0: (10 0c 32 42|42 32 0c 10) vminuh v0,v12,v6
[all …]
Daltivec2.d58 c0: (10 d1 84 03|03 84 d1 10) vabsdub v6,v17,v16
61 cc: (10 d1 a6 ad|ad a6 d1 10) vpermxor v6,v17,v20,v26
64 d8: (10 46 a8 7e|7e a8 46 10) vsubeuqm v2,v6,v21,v1
65 dc: (13 a6 01 3f|3f 01 a6 13) vsubecuq v29,v6,v0,v4
70 f0: (11 46 e0 c4|c4 e0 46 11) vrld v10,v6,v28
88 138: (10 d7 8c 88|88 8c d7 10) vpmsumw v6,v23,v17
89 13c: (12 86 cc c8|c8 cc 86 12) vpmsumd v20,v6,v25
93 14c: (13 bd 35 08|08 35 bd 13) vcipher v29,v29,v6
100 168: (10 73 35 4c|4c 35 73 10) vbpermq v3,v19,v6
123 1c4: (10 5f 36 c7|c7 36 5f 10) vcmpgtud\. v2,v31,v6
Daltivec3.d17 .*: (10 c9 b8 85|85 b8 c9 10) vrlwmi v6,v9,v23
53 .*: (10 42 37 c1|c1 37 42 10) bcdsr\. v2,v2,v6,1
69 .*: (12 de 36 02|02 36 de 12) vctzw v22,v6
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dattr-any-thumbv6.d1 # name: attributes for 'any' cpu v6 thumb insn
10 Tag_CPU_arch: v6
Dattr-names.d41 Tag_CPU_unaligned_access: v6
46 Tag_also_compatible_with: v6-M
Dmov-lowregs-any.d6 Tag_CPU_arch: v6
Darchv6s-m-bad.d1 #name: Valid v6S-M, invalid v6-M
Dattr-march-armv6j.d11 Tag_CPU_arch: v6
Dattr-march-armv6.d11 Tag_CPU_arch: v6
Dpr12198-1.d1 # name: PR12198 - Only select v6S-M when v6-M is selected (1)
Dattr-march-armv6s-m.d11 Tag_CPU_arch: v6-M
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-arm/
Dattr-merge-8a.s3 @ Tag_CPU_arch & Tag_CPU_arch_profile = v6-M
Dattr-merge-4a.s6 @ Tag_also_compatible_with = v6-M
Dattr-merge-4b.s3 @ Tag_CPU_arch = v6-M
Dattr-merge-4.attr10 Tag_also_compatible_with: v6-M
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/m68hc11/
D9s12x-mov.s13 v6=0x80
27 movb #v6, [a2,sp]

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