| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| D | alias.d | 75 10c: 0f08a448 sxtl v8.8h, v2.8b
76 110: 0f08a448 sxtl v8.8h, v2.8b
77 114: 4f08a448 sxtl2 v8.8h, v2.16b
78 118: 4f08a448 sxtl2 v8.8h, v2.16b
79 11c: 0f10a448 sxtl v8.4s, v2.4h
80 120: 0f10a448 sxtl v8.4s, v2.4h
81 124: 4f10a448 sxtl2 v8.4s, v2.8h
82 128: 4f10a448 sxtl2 v8.4s, v2.8h
83 12c: 0f20a448 sxtl v8.2d, v2.2s
84 130: 0f20a448 sxtl v8.2d, v2.2s
[all …]
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| D | no-aliases.d | 76 10c: 0f08a448 sshll v8.8h, v2.8b, #0
77 110: 0f08a448 sshll v8.8h, v2.8b, #0
78 114: 4f08a448 sshll2 v8.8h, v2.16b, #0
79 118: 4f08a448 sshll2 v8.8h, v2.16b, #0
80 11c: 0f10a448 sshll v8.4s, v2.4h, #0
81 120: 0f10a448 sshll v8.4s, v2.4h, #0
82 124: 4f10a448 sshll2 v8.4s, v2.8h, #0
83 128: 4f10a448 sshll2 v8.4s, v2.8h, #0
84 12c: 0f20a448 sshll v8.2d, v2.2s, #0
85 130: 0f20a448 sshll v8.2d, v2.2s, #0
[all …]
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| D | alias.s | 104 \s\()xtl v8.8h, v2.8b
105 \s\()shll v8.8h, v2.8b, #0
106 \s\()xtl2 v8.8h, v2.16b
107 \s\()shll2 v8.8h, v2.16b, #0
108 \s\()xtl v8.4s, v2.4h
109 \s\()shll v8.4s, v2.4h, #0
110 \s\()xtl2 v8.4s, v2.8h
111 \s\()shll2 v8.4s, v2.8h, #0
112 \s\()xtl v8.2d, v2.2s
113 \s\()shll v8.2d, v2.2s, #0
[all …]
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| D | neon-ins.d | 22 38: 4e011d08 mov v8.b\[0\], w8
23 3c: 4e011d08 mov v8.b\[0\], w8
82 128: 4e031d08 mov v8.b\[1\], w8
83 12c: 4e031d08 mov v8.b\[1\], w8
142 218: 4e051d08 mov v8.b\[2\], w8
143 21c: 4e051d08 mov v8.b\[2\], w8
202 308: 4e071d08 mov v8.b\[3\], w8
203 30c: 4e071d08 mov v8.b\[3\], w8
262 3f8: 4e091d08 mov v8.b\[4\], w8
263 3fc: 4e091d08 mov v8.b\[4\], w8
[all …]
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| D | neon-not.d | 36 70: 2e205908 mvn v8.8b, v8.8b
37 74: 2e205908 mvn v8.8b, v8.8b
38 78: 6e205908 mvn v8.16b, v8.16b
39 7c: 6e205908 mvn v8.16b, v8.16b
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| D | verbose-error.l | 75 [^:]*:26: Info: rev64 v8.8b,v9.8b
77 [^:]*:26: Info: rev64 v8.16b,v9.16b
78 [^:]*:26: Info: rev64 v8.4h,v9.4h
79 [^:]*:26: Info: rev64 v8.8h,v9.8h
80 [^:]*:26: Info: rev64 v8.2s,v9.2s
81 [^:]*:26: Info: rev64 v8.4s,v9.4s
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/ |
| D | altivec.d | 46 90: (11 1c 4b 00|00 4b 1c 11) vaddsbs v8,v28,v9
52 a8: (13 55 42 40|40 42 55 13) vadduhs v26,v21,v8
59 c4: (11 0f fd 82|82 fd 0f 11) vavgsw v8,v15,v31
92 148: (11 15 de 86|86 de 15 11) vcmpgtuw\. v8,v21,v27
97 15c: (10 00 41 8a|8a 41 00 10) vexptefp v0,v8
101 16c: (11 17 71 02|02 71 17 11) vmaxsb v8,v23,v14
121 1bc: (11 c8 79 4c|4c 79 c8 11) vmrglh v14,v8,v15
127 1d4: (11 28 6f e9|e9 6f 28 11) vmsumshs v9,v8,v13,v31
132 1e8: (10 32 43 48|48 43 32 10) vmulesh v1,v18,v8
136 1f8: (10 85 41 48|48 41 85 10) vmulosh v4,v5,v8
[all …]
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| D | altivec2.d | 53 ac: (7d 0c fd 4a|4a fd 0c 7d) stvfrx v8,r12,r31
63 d4: (11 e8 3e 3d|3d 3e e8 11) vaddecuq v15,v8,v7,v24
85 12c: (11 04 26 41|41 26 04 11) bcdsub\. v8,v4,v4,1
96 158: (12 68 cd 40|40 cd 68 12) vsubcuq v19,v8,v25
103 174: (12 28 ed c4|c4 ed 28 12) vsld v17,v8,v29
108 188: (13 a8 6e 82|82 6e a8 13) vshasigmaw v29,v8,0,13
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| D | power8.d | 53 ac: (11 4a 40 bd|bd 40 4a 11) vaddecuq v10,v10,v8,v2
54 b0: (10 af 44 fe|fe 44 af 10) vsubeuqm v5,v15,v8,v19
58 c0: (11 15 e0 c0|c0 e0 15 11) vaddudm v8,v21,v28
63 d4: (11 08 69 40|40 69 08 11) vaddcuq v8,v8,v13
73 fc: (10 a8 d6 01|01 d6 a8 10) bcdadd\. v5,v8,v26,1
95 154: (13 88 04 c7|c7 04 88 13) vcmpequd\. v28,v8,v0
99 164: (10 28 9e 8c|8c 9e 28 10) vmrgow v1,v8,v19
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| D | altivec3.d | 21 .*: (11 17 99 47|47 99 17 11) vcmpnezh v8,v23,v19
36 .*: (12 d9 44 07|07 44 d9 12) vcmpneb\. v22,v25,v8
40 .*: (10 a3 46 c1|c1 46 a3 10) bcds\. v5,v3,v8,1
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| /toolchain/binutils/binutils-2.27/opcodes/ |
| D | sparc-opc.c | 65 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ macro
790 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 },
791 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g…
792 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
793 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
794 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 },
795 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v8 },
815 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8 },
903 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */
904 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */
[all …]
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| D | arch7em-bad-2.d | 1 #name: Valid v8-M Mainline with DSP extension, invalid v8-M Baseline
|
| D | arch7em-bad-3.d | 1 #name: Valid v8-M Mainline with DSP extension, invalid v8-M Mainline
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| D | armv8-a-bad.d | 1 #name: Invalid v8-a
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| D | armv8-a-it-bad.d | 1 #name: Deprecated IT blocks (ARM v8)
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| D | armv8-2-fp16-simd-warning.d | 1 #name: Reject ARM v8.2 FP16 SIMD instruction for early arch
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| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-arm/ |
| D | attr-merge-10a.s | 3 @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M.BASE
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| D | attr-merge-8b.s | 3 @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M Baseline
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| D | attr-merge-10b.s | 3 @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M.MAIN
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| D | attr-merge-9b.s | 3 @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M Baseline
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| D | attr-merge-10b-dsp.s | 3 @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M.MAIN
|
| D | attr-merge-8.attr | 4 Tag_CPU_arch: v8-M.baseline
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| D | attr-merge-10.attr | 4 Tag_CPU_arch: v8-M.mainline
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| D | attr-merge-10-dsp.attr | 4 Tag_CPU_arch: v8-M.mainline
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sparc/ |
| D | synth.s | 1 # common (v8 or v9) synthetic insns
|