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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mmix/
Dround2-op.s1 # Two-operand variants of "R" and "I".
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/
Dsyntax.s1 # Test variants of assembler syntax.
Dsyntax.d2 #name: C6X syntax variants
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
Dand.s12 # case for nor, so we test all variants.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arc/
Dtaux.d4 # Most of the AUX rgisters are defined for all ARC variants besides the
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dgroup-reloc-ldr-parsing-bad.s5 @ No NC variants exist for the LDR relocations.
Dgroup-reloc-ldrs-parsing-bad.s5 @ No NC variants exist for the LDRS relocations.
Dvfp-neon-syntax-inc.s21 @ Test VFP vmov variants. These can all be conditional.
Dvfp1_t2.s1 @ VFP Instructions for D variants (Double precision)
Dvfp1.s1 @ VFP Instructions for D variants (Double precision)
Dvfp1xD_t2.s1 @ VFP Instructions for v1xD variants (Single precision only)
Dvfp1xD.s1 @ VFP Instructions for v1xD variants (Single precision only)
/toolchain/binutils/binutils-2.27/binutils/
Ddebug.c323 struct debug_method_variant_s **variants; member
1753 debug_method_variant *variants) in debug_make_method() argument
1761 m->variants = variants; in debug_make_method()
2762 for (j = 0; m->variants[j] != NULL; j++) in debug_write_class_type()
2766 v = m->variants[j]; in debug_write_class_type()
3332 || (m1->variants == NULL) != (m2->variants == NULL)) in debug_class_type_samep()
3334 if (m1->variants == NULL) in debug_class_type_samep()
3338 for (pv1 = m1->variants, pv2 = m2->variants; in debug_class_type_samep()
Dstabs.c2538 debug_method_variant *variants = NULL; in parse_stab_members() local
2587 variants = ((debug_method_variant *) in parse_stab_members()
2588 xmalloc (allocvars * sizeof *variants)); in parse_stab_members()
2790 variants = ((debug_method_variant *) in parse_stab_members()
2791 xrealloc (variants, in parse_stab_members()
2792 allocvars * sizeof *variants)); in parse_stab_members()
2796 variants[cvars] = debug_make_method_variant (dhandle, physname, in parse_stab_members()
2801 variants[cvars] = debug_make_static_method_variant (dhandle, in parse_stab_members()
2807 if (variants[cvars] == DEBUG_METHOD_VARIANT_NULL) in parse_stab_members()
2814 variants[cvars] = DEBUG_METHOD_VARIANT_NULL; in parse_stab_members()
[all …]
Dieee.c2551 debug_method_variant *variants; in ieee_read_cxx_class() member
3053 methods[methods_count].variants = NULL; in ieee_read_cxx_class()
3063 meth->variants = ((debug_method_variant *) in ieee_read_cxx_class()
3064 xrealloc (meth->variants, in ieee_read_cxx_class()
3066 * sizeof *meth->variants))); in ieee_read_cxx_class()
3069 meth->variants[meth->count] = mv; in ieee_read_cxx_class()
3071 meth->variants[meth->count] = DEBUG_METHOD_VARIANT_NULL; in ieee_read_cxx_class()
3172 methods[i].variants); in ieee_read_cxx_class()
/toolchain/binutils/binutils-2.27/config/
Dmmap.m442 # Systems known to be in this category are Windows (all variants),
/toolchain/binutils/binutils-2.27/opcodes/
DChangeLog-2004110 differences to earlier variants.
418 and ld variants.
478 variants in arch_mask. Only set m68881/68851 for 68k chips.
479 * m68k-op.c: Switch from ColdFire chips to core variants.
510 suffix. Use fmov*x macros, create all 3 fpsize variants in one
DChangeLog68 Remove Disp32S from non-64-bit variants. Remove Disp16 from
69 64-bit variants.
73 64-bit variants.
DChangeLog-201240 before parsing -M options. Handle more bfd_mach_ppc variants.
163 * arm-dis.c: Use preferred form of vrint instruction variants
319 variants.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/i860/
Dbitwise.s5 # Register forms (high variants do not have register forms).
/toolchain/binutils/binutils-2.27/gas/doc/
Dc-microblaze.texi15 The Xilinx MicroBlaze processor family includes several variants, all using
Dc-mips.texi118 On some MIPS variants there is a 32-bit mode flag; when this flag is
811 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
821 features. The resulting ABI variants are generally incompatible with each
831 The supported floating-point ABI variants are:
896 of GP and FP registers match and the special double-precision variants
901 @subsection Linking different FP ABI variants
906 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/cris/
Dbranch.s63 ; Ok, once more to make sure *all* 16-bit variants get ok for
/toolchain/binutils/binutils-2.27/gas/
DChangeLog-2006104 * doc/c-arm.texi: Fix spelling of ARMv7 profile variants.
1121 (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
1153 msr variants.
1201 (do_neon_cvt): Add support for VFP variants of instructions.
1204 vmov variants.
1607 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
2483 (do_t_mrs, do_t_msr): Validate V7M variants.
2484 (md_assemble): Check for NULL variants.
/toolchain/binutils/binutils-2.27/ld/
DChangeLog-2008104 Handle the two variants of pseudo-relocation.
106 Modify for the two pseudo_relocation variants.
982 * configure.tgt (xtensa*-*-*): Recognize processor variants.

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